公开(公告)号：US12131796B2

公开(公告)日：2024-10-29

申请号：US18195860

申请日：2023-05-10

Applicant: Rambus Inc.

Inventor： Yohan Frans

IPC: G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  H01L25/065

CPC classification number: G11C7/10 ,  G11C5/02 ,  G11C5/063 ,  G11C7/22 ,  G11C5/025 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/4824 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

公开(公告)号：US12131794B2

公开(公告)日：2024-10-29

申请号：US17893681

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui ,  Richard E. Fackenthal

IPC: G11C5/02 ,  G11C5/06 ,  G11C8/14 ,  H10B12/00

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  H10B12/488

Abstract: Methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. A memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. For example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include one or more gate material portions operable to modulate a conductivity between respective first and second portions. Each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material portions may couple the word lines with the respective second portion of the semiconductor material. Such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.

公开(公告)号：US12106801B2

公开(公告)日：2024-10-01

申请号：US17858376

申请日：2022-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon Jhy Liaw

IPC: G11C11/412 ,  G11C11/419 ,  G11C5/02 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C5/025 ,  G11C7/1096 ,  G11C7/12

Abstract: An array of memory cells is arranged into a plurality of columns and rows. A first signal line extends through a first column of the plurality of columns. The first signal line is electrically coupled to the memory cells in the first column. A first end portion of the first signal line is configured to receive a logic high signal from a first circuit during a first operational state of the memory device and a logic low signal from the first circuit during a second operational state of the memory device. A second circuit includes a plurality of transistors. The transistors are configured to be turned on or off to electrically couple a second end portion of the first signal line to a logic low source when the first end portion of the first signal line is configured to receive the logic low signal from the first circuit.

公开(公告)号：US20240324223A1

公开(公告)日：2024-09-26

申请号：US18731940

申请日：2024-06-03

Applicant: Lodestar Licensing Group LLC

Inventor： S. M. Istiaque Hossain ,  Prakash Rau Mokhna Rau ,  Arun Kumar Dhayalan ,  Damir Fazil ,  Joel D. Peterson ,  Anilkumar Chandolu ,  Albert Fayrushin ,  George Matamis ,  Christopher Larsen ,  Rokibul Islam

IPC: H10B43/27 ,  G11C5/02 ,  G11C5/06 ,  G11C16/04 ,  H01L21/768

CPC classification number: H10B43/27 ,  G11C5/025 ,  G11C5/06 ,  G11C16/0466 ,  H01L21/76802 ,  H01L21/76877

Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12094520B2

公开(公告)日：2024-09-17

申请号：US17584905

申请日：2022-01-26

Applicant: Micron Technology, Inc.

Inventor： Harish Gadamsetty ,  John A. Winegard

IPC: G11C11/4091 ,  G11C5/02 ,  G11C11/4074 ,  G11C11/408

CPC classification number: G11C11/4091 ,  G11C5/025 ,  G11C11/4074 ,  G11C11/4085

Abstract: A memory device, includes a memory partition. The memory partition includes a memory region comprising a memory element coupled to a wordline of the memory region, a sense amplifier region comprising a sense amplifier coupled to the memory element to sense a data state of the memory element, a sub-wordline region coupled to the wordline of the memory region, and a minigap region disposed at the intersection of the sub-wordline region and the sense amplifier region. The minigap includes a first plurality of transistors having a continuous layout in at least one direction across the minigap region with a second plurality of transistors of the sense amplifier region.

公开(公告)号：US20240257863A1

公开(公告)日：2024-08-01

申请号：US18584371

申请日：2024-02-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  John E. Linstadt ,  Thomas A. Giovannini ,  Scott C. Best ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

CPC classification number: G11C11/4093 ,  G11C5/025 ,  G11C5/063 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/824 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/12 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

公开(公告)号：US20240194645A1

公开(公告)日：2024-06-13

申请号：US18079631

申请日：2022-12-12

Applicant: XILINX, INC.

Inventor： Jay T. YOUNG ,  Davis Boyd MOORE ,  Sundeep Ram Gopal AGARWAL ,  Brian C. GAIDE

IPC: H01L25/065 ,  G11C5/02 ,  G11C5/06 ,  H01L23/48 ,  H01L27/02 ,  H01L27/06

CPC classification number: H01L25/0657 ,  G11C5/025 ,  G11C5/063 ,  H01L23/481 ,  H01L27/0207 ,  H01L27/0688 ,  H01L2225/06506

Abstract: An integrated circuit (IC) device includes a block of integrated circuitry that includes functional circuitry and configurable interface circuitry. The configurable interface circuitry includes output circuitry that routes a node of the functional circuitry to an output node of the block, and input circuitry that selectively routes the output node of the block or an input node of the block to the functional circuitry. The output circuitry may route a selectable subset of multiple nodes of the functional circuitry to respective output nodes of the block, and the input circuitry may be configured to route the output nodes of the block back to the functional circuitry in the absence of an adjacent block (e.g., to repurpose the output circuitry), or in addition to interfacing with the adjacent block.

公开(公告)号：US20240188288A1

公开(公告)日：2024-06-06

申请号：US18437665

申请日：2024-02-09

Applicant: Lodestar Licensing Group LLC

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Justin B. Dorhout

IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H01L21/768 ,  H01L23/00 ,  H01L23/538 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L21/76838 ,  H01L23/5386 ,  H01L24/14 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, the tiers individually comprising one of the conductive structures and one of the insulative structures, first support pillar structures extending through the stack structure within a first region of the microelectronic device, the first support pillar structures electrically isolated from a source structure underlying the stack structure, second support pillar structures extending through the stack structure within a second region of the microelectronic device, the second support pillar structures comprising an electrically conductive material in electrical communication with the source structure, and bridge structures extending between at least some neighboring first support pillar structures of the first support pillar structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20240172432A1

公开(公告)日：2024-05-23

申请号：US18428325

申请日：2024-01-31

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Yunfei Gao ,  Sanh D. Tang ,  Deepak Chandra Pandey

IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H10B43/27

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11990177B2

公开(公告)日：2024-05-21

申请号：US18195877

申请日：2023-05-10

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ming Li

IPC: G11C5/02 ,  G11C5/04 ,  G11C11/406 ,  G11C11/4093 ,  G11C11/4096 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/00

CPC classification number: G11C11/4093 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/406 ,  G11C11/4096 ,  H01L23/481 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/0401 ,  H01L2924/00011 ,  H01L2224/0401

Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.