公开(公告)号：US20240349498A1

公开(公告)日：2024-10-17

申请号：US18752438

申请日：2024-06-24

Applicant: Lodestar Licensing Group LLC

Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Nancy M. Lomeli

IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H01L23/538 ,  H10B43/27 ,  H10B43/50

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L23/5386 ,  H10B43/27 ,  H10B43/50

Abstract: A method of forming a microelectronic device comprises forming a sacrificial material over a base structure. Portions of the sacrificial material are replaced with an etch-resistant material. A stack structure is formed over the etch-resistant material and remaining portions of the sacrificial material. The stack structure comprises a vertically alternating sequence of insulative material and additional sacrificial material arranged in tiers, and at least one staircase structure horizontally overlapping the etch-resistant material and having steps comprising horizontal ends of the tiers. Slots are formed to vertically extend through the stack structure and the remaining portions of the sacrificial material. The sacrificial material and the additional sacrificial material are selectively replaced with conductive material after forming the slots to respectively form lateral contact structures and conductive structures. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20240324162A1

公开(公告)日：2024-09-26

申请号：US18734190

申请日：2024-06-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： You Che CHUANG ,  Chih-Ming LEE ,  Hsin-Chi CHEN ,  Hsun-Ying HUANG

IPC: H10B10/00 ,  G11C5/06

CPC classification number: H10B10/12 ,  G11C5/06

Abstract: A static random access memory (SRAM) cell includes a first pull-up (PU) transistor comprising a first gate structure. The SRAM cell further includes a second PU transistor comprising a second gate structure, wherein the second gate structure comprises a gate stack and gate spacers. The SRAM cell further includes a first butted contact, wherein the first butted contact electrically connects a first terminal of the first PU transistor to the second gate structure, wherein the first butted contact directly contacts each of a top surface and a sidewall of the gate stack.

公开(公告)号：US12100442B2

公开(公告)日：2024-09-24

申请号：US17682100

申请日：2022-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanho Kim ,  Daeseok Byeon ,  Hyunsurk Ryu

IPC: G11C11/4093 ,  G06N3/063 ,  G11C5/06 ,  G11C11/408 ,  G11C11/4094 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C11/4093 ,  G06N3/063 ,  G11C5/06 ,  G11C11/4082 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4094 ,  G11C16/0483 ,  G11C16/08

Abstract: Flash memory device includes: first pads to be bonded to external semiconductor chip, to receive at least one of command, address and control signals; second pads to be bonded to external semiconductor chip; memory cell array including memory cells; a row decoder block connected to memory cell array through word lines, to select one of word lines based on address provided to row decoder block; a buffer block to store command and address and provide address to row decoder block; a page buffer block connected to memory cell array through bit lines, connected to second pads through data lines without passing through buffer block, and configured to exchange data signals with external semiconductor chip through data lines and second pads; and a control logic block configured to receive command from buffer block, to receive control signals from external semiconductor chip, and to control row decoder block and page buffer block.

公开(公告)号：US20240312949A1

公开(公告)日：2024-09-19

申请号：US18306971

申请日：2023-04-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kang-Yun Yang ,  Yang-Tse Hung ,  Chao-Cheng Ku ,  Li-Yuan Lee

IPC: H01L23/00 ,  G11C5/06 ,  G11C16/14

CPC classification number: H01L24/49 ,  G11C5/06 ,  G11C16/14 ,  H01L2224/4912

Abstract: A layout structure of differential lines, a memory storage device and a memory control circuit unit are provided. The layout structure of the differential lines includes a wiring layer, a first wire and a second wire. The first wire is arranged on the wiring layer and configured to transmit a first differential signal. The second wire is arranged on the wiring layer and configured to transmit a second differential signal. A first end of the first wire and a first end of the second wire are coupled to a first electrical component. A second end of the first wire and a second end of the second wire are coupled to a second electrical component. The first end of the first wire has a first bending structure. One of the second end of the first wire and the second end of the second wire has a second bending structure.

公开(公告)号：US20240306384A1

公开(公告)日：2024-09-12

申请号：US18664547

申请日：2024-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hak Seon Kim ,  Byung Joo Go ,  Sung Kweon Baek ,  Jae Hwa Seo ,  Chang Heon Lee

IPC: H10B41/27 ,  G11C5/06 ,  H01L29/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L29/0653 ,  H10B43/27

Abstract: A semiconductor device comprises a substrate; an element isolation film that defines a first active region in the substrate; a first gate electrode on the first active region; a first source/drain region located inside the first active region between the element isolation film and the first gate electrode; and an isolation contact that extends in a vertical direction intersecting an upper face of the substrate, in the element isolation film. The isolation contact is configured to have a voltage applied thereto.

公开(公告)号：US12079146B2

公开(公告)日：2024-09-03

申请号：US17383056

申请日：2021-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghyeon Cho ,  Yongsuk Kwon ,  Kyungsoo Kim ,  Jonghoon Kim ,  Jonghyun Seok ,  Jonggeon Lee

IPC: H05K1/02 ,  G06F1/20 ,  G06F1/30 ,  G06F13/12 ,  G06F13/16 ,  G06F13/364 ,  G06F13/40 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  H05K1/14 ,  H05K1/16 ,  H05K1/18 ,  H05K3/36 ,  H05K7/02 ,  H05K7/20

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G06F13/409 ,  G11C5/06 ,  G11C7/1063

Abstract: A memory module includes a memory substrate including a main connector and an auxiliary connector, configured to be connected to an external device; and a plurality of memory chips mounted on at least one of a first surface or a second surface of the memory substrate, wherein the main connector is disposed on one side of the memory substrate, and the auxiliary connector is disposed on the second surface of the memory substrate.

公开(公告)号：US12075615B2

公开(公告)日：2024-08-27

申请号：US17205563

申请日：2021-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehun Jung ,  Suhwan Lim ,  Hyeyoung Kwon

IPC: H01L27/11556 ,  G11C5/06 ,  H01L23/538 ,  H01L27/11582 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L23/5386 ,  H10B43/27

Abstract: A semiconductor device includes a substrate, a stack structure including interlayer insulating layers and gate electrodes alternately and repeatedly stacked on the substrate in a first direction perpendicular, a channel structure that penetrates the stack structure, a contact plug disposed on the channel structure, and a bit line on the contact plug. The channel structure includes a core pattern, a pad structure on the core pattern, and a channel layer on a side surface of the core pattern and a side surface of the pad structure. The pad structure includes a pad pattern, a first pad layer, and a second pad layer, the first pad layer that is between the channel layer and the pad pattern, and the second pad layer including a first portion between the channel layer and the first pad layer, and a second portion between the first pad layer and the core pattern.

公开(公告)号：US12068053B2

公开(公告)日：2024-08-20

申请号：US17903889

申请日：2022-09-06

Applicant: KIOXIA CORPORATION

Inventor： Hideto Takekida

IPC: G11C5/06 ,  G11C16/08

CPC classification number: G11C5/06 ,  G11C16/08

Abstract: A semiconductor device includes a substrate, a first external connection pad separated from the substrate in a first direction, which is a thickness direction thereof, a first coil separated from the substrate in the first direction and electrically connected to the connection pad, a first stacked body between the connection pad and the substrate and between the first coil and the substrate, the first stacked body including a first insulator, a first wiring therein, and a first pad electrically connected to the wiring, and a second stacked body between the first stacked body and the substrate, the second stacked body including a second insulator, a second wiring therein, a second pad electrically connected to the second wiring, and a second coil. The first insulator contacts the second insulator. The first pad contacts the second pad. A part of the first coil overlaps the second coil in the first direction.

公开(公告)号：US20240276639A1

公开(公告)日：2024-08-15

申请号：US18604133

申请日：2024-03-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan

IPC: H05K1/11 ,  G06F1/18 ,  G06F13/16 ,  G06F13/40 ,  G06F15/78 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4093 ,  H05K1/18

CPC classification number: H05K1/11 ,  G06F1/184 ,  G06F13/1694 ,  G06F13/4068 ,  G06F15/7803 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4082 ,  G11C11/4093 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

公开(公告)号：US20240268109A1

公开(公告)日：2024-08-08

申请号：US18638859

申请日：2024-04-18

Applicant: KIOXIA CORPORATION

Inventor： Yusuke SHIMA

IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/67 ,  H01L21/768 ,  H01L29/04 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/67075 ,  H01L21/76876 ,  H01L29/04 ,  H10B43/27

Abstract: A semiconductor memory device includes a first region where a plurality of conductive layers, a plurality of insulating layers, a semiconductor layer, and a gate insulating layer are formed and a second region different from the first region above a substrate. The plurality of conductive layers include a plurality of first conductive layers and a plurality of second conductive layers. The semiconductor memory device includes a plurality of first films different from the first conductive layers disposed in same layers as the plurality of first conductive layers in the second region and a plurality of second films different from the second conductive layers and the first films disposed in same layers as the plurality of second conductive layers in the second region.