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公开(公告)号：US20240349498A1
公开(公告)日：2024-10-17
申请号：US18752438
申请日：2024-06-24
摘要： A method of forming a microelectronic device comprises forming a sacrificial material over a base structure. Portions of the sacrificial material are replaced with an etch-resistant material. A stack structure is formed over the etch-resistant material and remaining portions of the sacrificial material. The stack structure comprises a vertically alternating sequence of insulative material and additional sacrificial material arranged in tiers, and at least one staircase structure horizontally overlapping the etch-resistant material and having steps comprising horizontal ends of the tiers. Slots are formed to vertically extend through the stack structure and the remaining portions of the sacrificial material. The sacrificial material and the additional sacrificial material are selectively replaced with conductive material after forming the slots to respectively form lateral contact structures and conductive structures. Microelectronic devices, memory devices, and electronic systems are also described.
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公开(公告)号：US12002759B2
公开(公告)日：2024-06-04
申请号：US17660669
申请日：2022-04-26
发明人： Jordan D. Greenlee , Lifang Xu , Rita J. Klein , Xiao Li , Everett A. McTeer
IPC分类号： H01L23/532 , H01L21/768 , H01L23/00 , H01L23/522 , H10B41/27 , H10B41/41
CPC分类号： H01L23/53266 , H01L21/76846 , H01L23/5226 , H01L23/562 , H10B41/27 , H10B41/41
摘要： An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.
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3.发明公开公开(公告)号：US20240153877A1
公开(公告)日：2024-05-09
申请号：US18402618
申请日：2024-01-02
发明人： Jordan D. Greenlee , John D. Hopkins , Rita J. Klein , Everett A. McTeer , Lifang Xu , Daniel Billingsley , Collin Howder
IPC分类号： H01L23/535 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35
CPC分类号： H01L23/535 , H01L21/76805 , H01L21/76816 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/5283 , H01L23/53257 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35
摘要： A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
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公开(公告)号：US11923415B2
公开(公告)日：2024-03-05
申请号：US17890565
申请日：2022-08-18
摘要： Some embodiments include an integrated assembly having a source structure. The source structure includes, in ascending order, a first conductively-doped semiconductor material, one or more first insulative layers, a second conductively-doped semiconductor material, one or more second insulative layers, and a third conductively-doped semiconductor material. The source structure includes blocks extending through the second conductively-doped semiconductor material. Conductive levels are over the source structure. Channel material extends vertically along the conductive levels, and extends into the source structure to be in direct contact with the second conductively-doped semiconductor material. One or more memory cell materials are between the channel material and the conductive levels. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号：US20240057335A1
公开(公告)日：2024-02-15
申请号：US18384455
申请日：2023-10-27
CPC分类号： H10B43/27 , H01L21/31111 , H01L21/02636 , H01L21/0217 , H01L21/02164 , H01L21/02129 , H01L29/40117 , H01L29/40114 , H10B41/10 , H10B41/27 , H10B43/10
摘要： Some embodiments include an integrated assembly having a second deck over a first deck. The first deck has first memory cell levels, and the second deck has second memory cell levels. A pair of cell-material-pillars pass through the first and second decks. Memory cells are along the first and second memory cell levels. The cell-material-pillars are a first pillar and a second pillar. An intermediate level is between the first and second decks. The intermediate level includes a region between the first and second pillars. The region includes a first segment adjacent the first pillar, a second segment adjacent the second pillar, and a third segment between the first and second segments. The first and second segments include a first composition, and the third segment includes a second composition different from the first composition. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号：US20240290722A1
公开(公告)日：2024-08-29
申请号：US18652551
申请日：2024-05-01
发明人： Jordan D. Greenlee , Lifang Xu , Rita J. Klein , Xiao Li , Everett A. McTeer
IPC分类号： H01L23/532 , H01L21/768 , H01L23/00 , H01L23/522 , H10B41/27 , H10B41/41
CPC分类号： H01L23/53266 , H01L21/76846 , H01L23/5226 , H01L23/562 , H10B41/27 , H10B41/41
摘要： An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.
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公开(公告)号：US12063782B2
公开(公告)日：2024-08-13
申请号：US17941900
申请日：2022-09-09
IPC分类号： H10B43/27 , H01L21/02 , H01L21/28 , H01L21/285 , H01L21/311 , H01L29/66 , H10B41/10 , H10B41/27 , H10B43/10
CPC分类号： H10B43/27 , H01L21/02164 , H01L21/0217 , H01L21/02532 , H01L21/28518 , H01L21/31111 , H01L29/40114 , H01L29/40117 , H01L29/66545 , H10B41/10 , H10B41/27 , H10B43/10
摘要： Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.
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8.发明授权公开(公告)号：US12096633B2
公开(公告)日：2024-09-17
申请号：US17517459
申请日：2021-11-02
CPC分类号： H10B43/27 , H01L21/02164 , H01L21/0217 , H01L21/02636 , H01L21/31111 , H10B41/10 , H10B41/27 , H10B43/10 , H01L29/66545
摘要： A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Upper masses comprise first material laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks and second material laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory blocks longitudinally-between and under the upper masses. The second material is of different composition from that of the first material. The second material comprises insulative material. Other embodiments, including method, are disclosed.
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公开(公告)号：US11990528B2
公开(公告)日：2024-05-21
申请号：US18083428
申请日：2022-12-16
发明人： David Ross Economy , Rita J. Klein , Jordan D. Greenlee , John Mark Meldrim , Brenda D. Kraus , Everett A. McTeer
摘要： Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.
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