公开(公告)号：US12096633B2

公开(公告)日：2024-09-17

申请号：US17517459

申请日：2021-11-02

Applicant: Lodestar Licensing Group LLC

Inventor： Jordan D. Greenlee ,  Daniel Billingsley ,  Indra V. Chary ,  Rita J. Klein

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/311 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H01L29/66

CPC classification number: H10B43/27 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02636 ,  H01L21/31111 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H01L29/66545

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Upper masses comprise first material laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks and second material laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory blocks longitudinally-between and under the upper masses. The second material is of different composition from that of the first material. The second material comprises insulative material. Other embodiments, including method, are disclosed.

公开(公告)号：US12094721B2

公开(公告)日：2024-09-17

申请号：US16959692

申请日：2019-01-03

Applicant: University of Maryland, College Park

Inventor： Gary W. Rubloff ,  Sang Bok Lee ,  Keith Gregorczyk

IPC: H01M4/08 ,  C23C14/04 ,  C23C16/04 ,  H01L21/02 ,  H01L21/32 ,  H01L21/3205 ,  H01L49/02 ,  H01M4/04 ,  H01M6/40 ,  H01L31/0224 ,  H01L31/0445 ,  H01L33/08 ,  H01L33/38 ,  H10N30/30 ,  H10N30/50

CPC classification number: H01L21/32 ,  C23C14/042 ,  C23C16/042 ,  H01L21/02636 ,  H01L21/3205 ,  H01L28/87 ,  H01M4/0423 ,  H01M4/0428 ,  H01M4/08 ,  H01M6/40 ,  H01L31/022425 ,  H01L31/0445 ,  H01L33/08 ,  H01L33/38 ,  H10N30/302 ,  H10N30/50

Abstract: A solid-state device includes a substrate with a stack of constituent thin-film layers that define an arrangement of electrodes and intervening layers. The constituent layers can conform to or follow a non-planar surface of the substrate, thereby providing a 3-D non-planar geometry to the stack. Fabrication employs a common shadow mask moved between lateral positions offset from each other to sequentially form at least some of the layers in the stack, whereby layers with a similar function (e.g., anode, cathode, etc.) can be electrically connected together at respective edge regions. Wiring layers can be coupled to the edge regions for making electrical connection to the respective subset of layers, thereby simplifying the fabrication process. By appropriate selection and deposition of the constituent layers, the multi-layer device can be configured as an energy storage device, an electro-optic device, a sensing device, or any other solid-state device.

公开(公告)号：US12027607B2

公开(公告)日：2024-07-02

申请号：US17843968

申请日：2022-06-18

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Matthias Bauer ,  Naved Ahmed Siddiqui ,  Phillip Stout

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/78696

Abstract: Electronic devices and methods of forming electronic devices with gate-all-around non-I/O devices and finlike structures for I/O devices are described. A plurality of dummy gates is etched to expose a fin comprising alternating layers of a first material and a second material. The second material layers are removed to create openings and the first material layers remaining are epitaxially grown to form a finlike structure.

公开(公告)号：US11955532B2

公开(公告)日：2024-04-09

申请号：US17080713

申请日：2020-10-26

Applicant: Intel Corporation

Inventor： Jeffrey S. Leib ,  Jenny Hu ,  Anindya Dasgupta ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H01L49/02 ,  H10B10/00 ,  H01L23/00

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.

公开(公告)号：US11948796B2

公开(公告)日：2024-04-02

申请号：US17616131

申请日：2020-06-10

Applicant: Applied Materials, Inc.

Inventor： Yi-Chiau Huang ,  Chen-Ying Wu ,  Abhishek Dube ,  Chia Cheng Chin ,  Saurabh Chopra

IPC: C30B25/10 ,  C23C16/06 ,  C30B25/18 ,  C30B29/52 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L21/02636 ,  C23C16/06 ,  C30B25/18 ,  C30B29/52 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/823418 ,  H01L29/0847 ,  H01L21/02381 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/823431 ,  H01L29/785

Abstract: One or more embodiments described herein relate to selective methods for fabricating devices and structures. In these embodiments, the devices are exposed inside the process volume of a process chamber. Precursor gases are flowed in the process volume at certain flow ratios and at certain process conditions. The process conditions described herein result in selective epitaxial layer growth on the {100} planes of the crystal planes of the devices, which corresponds to the top of each of the fins. Additionally, the process conditions result in selective etching of the {110} plane of the crystal planes, which corresponds to the sidewalls of each of the fins. As such, the methods described herein provide a way to grow or etch epitaxial films at different crystal planes. Furthermore, the methods described herein allow for simultaneous epitaxial film growth and etch to occur on the different crystal planes.

公开(公告)号：US20240097034A1

公开(公告)日：2024-03-21

申请号：US18522461

申请日：2023-11-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Lin Lee ,  Chih-Hao Chang ,  Chih-Hsin Ko ,  Feng Yuan ,  Jeff J. Xu

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/31 ,  H01L21/311 ,  H01L21/76 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/1608

Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

公开(公告)号：US11923200B2

公开(公告)日：2024-03-05

申请号：US17824545

申请日：2022-05-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Hsien Huang ,  Yi-Fang Pai ,  Chien-Chang Su

IPC: H01L21/02 ,  H01L21/20 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/417

CPC classification number: H01L21/20 ,  H01L21/02636 ,  H01L29/0692 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/7848

Abstract: An integrated circuit includes a gate structure over a substrate. The integrated circuit includes a first silicon-containing material structure in a recess. The first silicon-containing material structure includes a first layer below a top surface of the substrate and in direct contact with the substrate. The first silicon-containing material structure includes a second layer over the first layer, wherein an entirety of the second layer is above the top surface of the substrate, a first region of the second layer closer to the gate structure is thinner than a second region of the second layer farther from the gate structure. The first silicon-containing material structure includes a third layer between the first layer and the second layer, wherein at least a portion of the third layer is below the top surface of the substrate.

公开(公告)号：US20240038594A1

公开(公告)日：2024-02-01

申请号：US18115302

申请日：2023-02-28

Applicant: TESSERA LLC

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L29/417 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/823481 ,  H01L29/0649 ,  H01L29/785 ,  H01L29/41791 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/6653

Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

公开(公告)号：US11889695B2

公开(公告)日：2024-01-30

申请号：US17504313

申请日：2021-10-18

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Justin B. Dorhout ,  Indra V. Chary ,  Jun Fang ,  Matthew Park ,  Zhiqiang Xie ,  Scott D. Stull ,  Daniel Osterberg ,  Jason Reece ,  Jian Li

IPC: H01L27/11582 ,  H10B43/27 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L21/02 ,  H01L29/10 ,  H01L23/522 ,  H10B41/27 ,  H10B43/50 ,  H10B41/35 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5226 ,  H01L29/1037 ,  H10B41/27 ,  H10B41/35 ,  H10B43/50 ,  H10B43/10

Abstract: A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed.

公开(公告)号：US20240015968A1

公开(公告)日：2024-01-11

申请号：US18370543

申请日：2023-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji KANAMORI ,  Shinhwan KANG

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H10B43/10 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/528 ,  H01L21/02667 ,  H01L21/31144 ,  H01L29/40117 ,  H01L21/31111 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02636 ,  H01L21/31116 ,  H10B43/10 ,  H10B43/40 ,  H10B43/50

Abstract: A vertical memory device including gate electrodes on a substrate, the gate electrodes being spaced apart in a first direction and stacked in a staircase arrangement; a channel extending through the gate electrodes in the first direction; a first contact plug extending through a pad of a first gate electrode to contact an upper surface of the first gate electrode, the first contact plug extending through a portion of a second gate electrode, and the second gate electrode being adjacent to the first gate electrode; a first spacer between the first contact plug and sidewalls of the first gate electrode and the second gate electrode facing the first contact plug, the first spacer electrically insulating the first contact plug from the second gate electrode; and a first burying pattern contacting bottom surfaces of the first contact plug and the first spacer, the first burying pattern including an insulating material.