公开(公告)号：US11791409B2

公开(公告)日：2023-10-17

申请号：US18093445

申请日：2023-01-05

申请人： Key Foundry Co., Ltd.

发明人： Jin Seong Chung ,  Tae Hoon Lee

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/7835 ,  H01L29/063 ,  H01L29/0623 ,  H01L29/0856 ,  H01L29/0886 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816

摘要： A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

公开(公告)号：US09711640B2

公开(公告)日：2017-07-18

申请号：US15081069

申请日：2016-03-25

申请人： STMICROELECTRONICS S.R.L.

发明人： Davide Giuseppe Patti ,  Antonio Giuseppe Grimaldi

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L29/063 ,  H01L29/0856 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66734

摘要： A vertical conduction integrated electronic device including: a semiconductor body; a trench that extends through part of the semiconductor body and delimits a portion of the semiconductor body, which forms a first conduction region having a first type of conductivity and a body region having a second type of conductivity, which overlies the first conduction region; a gate region of conductive material, which extends within the trench; an insulation region of dielectric material, which extends within the trench and is arranged between the gate region and the body region; and a second conduction region, which overlies the body region. The second conduction region is formed by a conductor.

公开(公告)号：US20160372572A1

公开(公告)日：2016-12-22

申请号：US14771089

申请日：2014-12-04

申请人： Shuk-Wa FUNG

发明人： Shuk-Wa FUNG ,  Xianda ZHOU ,  Johnny Kin On SIN

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L21/3065 ,  H01L21/265 ,  H01L21/324 ,  H01L21/285 ,  H01L29/739 ,  H01L29/08

CPC分类号： H01L29/66348 ,  H01L21/265 ,  H01L21/28556 ,  H01L21/3065 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0856 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66295 ,  H01L29/66333 ,  H01L29/6634 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/7813

摘要： Provided in the present invention is a trench gate power MOSFET (TMOS/UMOS) structure with a heavily doped polysilicon source region. The polysilicon source region is formed by deposition, and a trench-shaped contact hole is used at the source region, in order to attain low contact resistance and small cell pitch. The present invention may also be implemented in an IGBT.

摘要翻译： 在本发明中提供的是具有重掺杂多晶硅源极区域的沟槽栅功率MOSFET（TMOS / UMOS）结构。 通过沉积形成多晶硅源极区域，并且在源极区域使用沟槽形接触孔，以获得低接触电阻和小的电池间距。 本发明也可以在IGBT中实现。

公开(公告)号：US20160064497A1

公开(公告)日：2016-03-03

申请号：US14840744

申请日：2015-08-31

申请人： MaxPower Semiconductor Inc.

发明人： Mohamed N. Darwish ,  Jun Zeng

IPC分类号： H01L29/40 ,  H03K17/687 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/16

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0856 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7813 ,  H01L29/7823 ,  H01L29/7827 ,  H01L29/7835 ,  H03K17/687

摘要： N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).

摘要翻译： 其中绝缘场板耦合到漂移区的N沟道功率半导体器件，并且固定静电电荷也存在于漂移区和场板周围的绝缘体之间的界面处。 除了在漏极区附近发生的电压降（由于场板的存在）外，静电电荷还允许在源极区域附近发生OFF状态电压降。

公开(公告)号：US09147594B2

公开(公告)日：2015-09-29

申请号：US13910633

申请日：2013-06-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tsung-Lin Lee ,  Chih-Hao Chang ,  Chih-Hsin Ko ,  Feng Yuan ,  Jeff J. Xu

IPC分类号： H01L29/66 ,  H01L21/76 ,  H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A field effect transistor including a substrate which includes, a fin structure, the fin structure having a top surface. The field effect transistor further including an isolation in the substrate and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the fin structure and the isolation structure. The S/D recess cavity includes a lower portion, the lower portion further includes a first strained layer, a first dielectric film and a second dielectric film, wherein the first strained layer is disposed between the first dielectric film and the second dielectric film. The S/D recess cavity further includes an upper portion including a second strained layer overlying the first strained layer, wherein a ratio of a height of the upper portion to a height of the lower portion ranges from about 0.8 to about 1.2.

摘要翻译： 一种场效应晶体管，其包括基板，该基板包括翅片结构，所述翅片结构具有顶表面。 所述场效应晶体管还包括在所述衬底中的隔离以及设置在所述鳍结构和所述隔离结构之间的所述衬底的顶表面下方的源极/漏极（S / D）凹陷腔。 S / D凹部空腔包括下部，下部还包括第一应变层，第一介电膜和第二介电膜，其中第一应变层设置在第一介电膜和第二介电膜之间。 S / D凹部空腔还包括上部，其包括覆盖在第一应变层上的第二应变层，其中上部的高度与下部的高度的比率在约0.8至约1.2的范围内。

公开(公告)号：US20150187921A1

公开(公告)日：2015-07-02

申请号：US14273159

申请日：2014-05-08

申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.

发明人： Jae Hoon PARK ,  In Hyuk SONG ,  Dong Soo SEO ,  Ji Yeon OH ,  Kee Ju UM

IPC分类号： H01L29/739 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L29/7397 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/1025 ,  H01L29/1095 ,  H01L29/267 ,  H01L29/7802 ,  H01L29/7813

摘要： A power semiconductor device may include a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type and formed in an upper portion of the first semiconductor region; a third semiconductor region having a first conductivity type and formed in an upper portion of the second semiconductor region; and a trench gate formed by penetrating from the third semiconductor region to the first semiconductor region. A portion of at least one of the first semiconductor region, the second semiconductor region, and the third semiconductor region may include a device protection material of which a conduction band has a main state and a satellite state in an E-k diagram, and a curvature of the device protection material in the satellite state may be lower than a curvature thereof in the main state in the E-k diagram.

摘要翻译： 功率半导体器件可以包括具有第一导电类型的第一半导体区域; 具有第二导电类型并形成在第一半导体区域的上部的第二半导体区域; 具有第一导电类型并形成在第二半导体区域的上部的第三半导体区域; 以及通过从第三半导体区域穿透到第一半导体区域而形成的沟槽栅极。 第一半导体区域，第二半导体区域和第三半导体区域中的至少一个的一部分可以包括在Ek图中导带具有主状态和卫星状态的器件保护材料，以及曲率 处于卫星状态的器件保护材料可能低于Ek图中主状态下的曲率。

公开(公告)号：US20150111354A1

公开(公告)日：2015-04-23

申请号：US14580730

申请日：2014-12-23

申请人： Icemos Technology Ltd.

发明人： Samuel ANDERSON ,  Takeshi ISHIGURO

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/417

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0856 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7308 ,  H01L29/7371 ,  H01L29/7393 ,  H01L29/74 ,  H01L29/861

摘要： Superjunction semiconductor devices having narrow surface layout of terminal structures and methods of manufacturing the devices are provided. The narrow surface layout of terminal structures is achieved, in part, by connecting a source electrode to a body contact region within a semiconductor substrate at a body contact interface comprising at least a first side of the body contact region other than a portion of a first main surface of the semiconductor substrate.

摘要翻译： 提供具有端子结构的窄表面布局的超结半导体器件和制造器件的方法。 端子结构的窄表面布局部分地通过在源体接触界面处将源电极连接到半导体衬底内的体接触区域而实现，所述体接触界面包括至少第一侧的身体接触区域，而不是第一 半导体衬底的主表面。

公开(公告)号：US20140339630A1

公开(公告)日：2014-11-20

申请号：US14329806

申请日：2014-07-11

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Hamza Yilmaz ,  Madhur Bobde ,  Hong Chang ,  Yeeheng Lee ,  Daniel Calafut ,  Jongoh Kim ,  Sik Lui ,  John Chen

IPC分类号： H01L29/78 ,  H01L29/423

CPC分类号： H01L29/7813 ,  H01L27/0251 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/6656 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7827

摘要： Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers that are formed along the sidewall of the gate caps. Additionally, the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The two-step gate oxide combined with the self-aligned source contacts allow for the production of devices with a pitch in the deep sub-micron level. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 本公开的方面描述了具有自对准源触点的高密度沟槽基功率MOSFET和用于制造这种器件的方法。 源触点与沿着栅极盖的侧壁形成的间隔物自对准。 另外，有源器件可以具有两步栅极氧化物。 下部可以具有比栅极氧化物的上部的厚度大的厚度。 与自对准源触点结合的两步栅极氧化物允许生产具有深亚微米级的间距的器件。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US08581298B2

公开(公告)日：2013-11-12

申请号：US12724243

申请日：2010-03-15

申请人： Mitsuhiko Kitagawa

发明人： Mitsuhiko Kitagawa

IPC分类号： H01L29/74

CPC分类号： H01L27/088 ,  H01L29/0634 ,  H01L29/0856 ,  H01L29/0878 ,  H01L29/4236 ,  H01L29/7391 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7828 ,  H01L29/7831 ,  H01L29/7838

摘要： A semiconductor device includes: a semiconductor layer having a first end portion and a second end portion; a first main electrode provided on the first end portion and electrically connected to the semiconductor layer; a second main electrode provided on the second end portion and electrically connected to the semiconductor layer; a first gate electrode provided via a first gate insulating film in a plurality of first trenches formed from the first end portion toward the second end portion; and a second gate electrode provided via a second gate insulating film in a plurality of second trenches formed from the second end portion toward the first end portion. Spacing between a plurality of the first gate electrodes and spacing between a plurality of the second gate electrodes are 200 nm or less.

摘要翻译： 半导体器件包括：具有第一端部和第二端部的半导体层; 第一主电极，设置在第一端部上并与半导体层电连接; 第二主电极，设置在第二端部并与半导体层电连接; 第一栅电极，其经由第一栅极绝缘膜设置在由所述第一端部朝向所述第二端部形成的多个第一沟槽中; 以及第二栅电极，其经由第二栅极绝缘膜设置在由所述第二端部朝向所述第一端部形成的多个第二沟槽中。 多个第一栅电极之间的间隔和多个第二栅电极之间的间隔为200nm以下。

公开(公告)号：US20130221498A1

公开(公告)日：2013-08-29

申请号：US13601952

申请日：2012-08-31

申请人： Hirokazu HAYASHI

发明人： Hirokazu HAYASHI

IPC分类号： H01L29/02 ,  H01L21/20

CPC分类号： H01L29/7813 ,  H01L29/04 ,  H01L29/0856 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734

摘要： A semiconductor device having a trench gate structure is formed by self alignment. The manufacturing method of the semiconductor device includes: forming a control electrode in an interior of trenches, etching a semiconductor layer between adjacent trenches to form an opening having a depth that is about level with an upper end of the control electrode with a portion of the semiconductor layer remaining between the opening and the control electrode, forming a first semiconductor region of the second conductive type from the surface of the semiconductor layer to a depth above the lower end of the control electrode, forming a single crystallized conductive layer from the first semiconductor region and the portion of the semiconductor layer, and forming a second semiconductor region, the second semiconductor region including the portion of the semiconductor layer and the single crystallized portion of the conductive layer.

摘要翻译： 具有沟槽栅极结构的半导体器件通过自对准形成。 半导体器件的制造方法包括：在沟槽内部形成控制电极，蚀刻相邻沟槽之间的半导体层，以形成具有与控制电极的上端大致水平的深度的开口，其中一部分 半导体层保持在开口和控制电极之间，从半导体层的表面形成第二导电类型的第一半导体区域到控制电极的下端的深度，从第一半导体形成单个晶体化导电层 区域和半导体层的部分，并且形成第二半导体区域，第二半导体区域包括半导体层的部分和导电层的单个结晶部分。