公开(公告)号：US11411177B2

公开(公告)日：2022-08-09

申请号：US16879577

申请日：2020-05-20

申请人： STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

发明人： Philippe Boivin ,  Daniel Benoit ,  Remy Berthelon

IPC分类号： H01L29/02 ,  H01L45/00 ,  H01L27/24

摘要： The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.

公开(公告)号：US11029203B2

公开(公告)日：2021-06-08

申请号：US16544718

申请日：2019-08-19

申请人： PsiQuantum Corp.

发明人： Faraz Najafi ,  Syrus Ziai

IPC分类号： G01J1/42 ,  G01J1/44 ,  G01J1/04 ,  H01L29/02 ,  H01L31/08

摘要： An electronic device includes a first superconducting wire (with a first end and a second end) having a first threshold superconducting current. The device includes a second superconducting wire (with a first end and a second end) having a second threshold superconducting current that is less than the first threshold superconducting current. The second end of the first superconducting wire and the second end of the second superconducting wire are coupled to a common voltage node. A resistor is coupled between the first superconducting wire and the second superconducting wire, with a first end of the resistor coupled to the first end of the first superconducting wire and a second end of the resistor coupled to the first end of the second superconducting wire. The device includes a current source coupled with the first superconducting wire, and coupled with a combination of the resistor and the second superconducting wire.

公开(公告)号：US10453849B2

公开(公告)日：2019-10-22

申请号：US15936396

申请日：2018-03-26

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang ,  Sho-Shen Lee

IPC分类号： H01L29/02 ,  H01L27/108 ,  G11C11/401

摘要： The present invention provides a dynamic random access memory structure, comprising a substrate defining a cell region and a peripheral region on the substrate, a shallow trench isolation structure located in the peripheral region adjacent to the cell region, wherein the shallow trench isolation structure has a concave top surface, a first dummy bit line gate located within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate located in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.

公开(公告)号：US10256290B2

公开(公告)日：2019-04-09

申请号：US15802425

申请日：2017-11-02

申请人： Comptek Solutions Oy

发明人： Pekka Laukkanen ,  Jouko Lang ,  Marko Punkkinen ,  Marjukka Tuominen ,  Veikko Tuominen ,  Johnny Dahl ,  Juhani Vayrynen

IPC分类号： H01L29/02 ,  H01L21/02 ,  H01L21/28 ,  H01L21/316 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L21/324 ,  H01L29/201

摘要： A method for treating a compound semiconductor substrate, in which method in vacuum conditions a surface of an In-containing III-As, III-Sb or III-P substrate is cleaned from amorphous native oxides and after that the cleaned substrate is heated to a temperature of about 250-550° C. and oxidized by introducing oxygen gas onto the surface of the substrate. The invention relates also to a compound semiconductor substrate, and the use of the substrate in a structure of a transistor such as MOSFET.

公开(公告)号：US10163621B1

公开(公告)日：2018-12-25

申请号：US15609775

申请日：2017-05-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jin Cai

IPC分类号： H01G4/018 ,  H01L21/02 ,  H01L29/66 ,  H01L33/00 ,  H01L27/088 ,  H01L31/113 ,  H01L21/8238 ,  H01L29/02

摘要： A semiconductor device and a method of forming the same are disclosed. The method includes receiving a semiconductor substrate and a fin extending from the semiconductor substrate; forming multiple dielectric layers conformally covering the fin, the multiple dielectric layers including a first charged dielectric layer having net fixed first-type charges and a second charged dielectric layer having net fixed second-type charges, the second-type charges being opposite to the first-type charges, the first-type charges having a first sheet density and the second-type charges having a second sheet density, the first charged dielectric layer being interposed between the fin and the second charged dielectric layer; patterning the multiple dielectric layers, thereby exposing a first portion of the fin, wherein a second portion of the fin is surrounded by at least a portion of the first charged dielectric layer; and forming a gate structure engaging the first portion of the fin.

公开(公告)号：US10115771B2

公开(公告)日：2018-10-30

申请号：US15791514

申请日：2017-10-24

申请人： Toshiba Memory Corporation

发明人： Takuya Konno

IPC分类号： H01L29/02 ,  H01L27/24 ,  G11C13/00 ,  H01L45/00

摘要： According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.

公开(公告)号：US10008169B2

公开(公告)日：2018-06-26

申请号：US15646452

申请日：2017-07-11

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Hiroyuki Miyake ,  Hideaki Shishido ,  Ryo Arasawa

IPC分类号： G09G3/36 ,  G06F3/038 ,  H01L27/12 ,  H01L29/02

CPC分类号： G09G3/3648 ,  G06F1/3265 ,  G06F3/038 ,  G09G3/3614 ,  H01L27/1225 ,  H01L29/02 ,  Y02D10/153

摘要： An object is to provide a driving method of a liquid crystal display device with a low power consumption and a high image quality. A pixel includes a liquid crystal element and a transistor which controls supply of an image signal to the liquid crystal element. The transistor includes, in a channel formation region, a semiconductor which has a wider band gap than a silicon semiconductor and has a lower intrinsic carrier density than silicon, and has an extremely low off-state current. In inversion driving of pixels, image signals having opposite polarities are input to a pair of signal lines between which a pixel electrode is disposed. By employing such a structure, the quality of the displayed image can be increased even in the absence of a capacitor in the pixel.

公开(公告)号：US09985096B2

公开(公告)日：2018-05-29

申请号：US15208186

申请日：2016-07-12

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Sanjay C. Mehta ,  Xin Miao ,  Chun-Chen Yeh

IPC分类号： H01L29/10 ,  H01L29/02 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/324 ,  H01L29/08 ,  H01L21/02

CPC分类号： H01L29/0638 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66537 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7851

摘要： A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.

公开(公告)号：US09865676B2

公开(公告)日：2018-01-09

申请号：US15359209

申请日：2016-11-22

申请人： Macroblock, Inc.

发明人： Chih-Fang Huang ,  Kung-Yen Lee ,  Chia-Hui Cheng ,  Sheng-Zhong Wang

IPC分类号： H01L29/02 ,  H01L29/06 ,  H01L29/36 ,  H01L29/423 ,  H01L29/78 ,  H01L29/08

CPC分类号： H01L29/0619 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/36 ,  H01L29/42356 ,  H01L29/7811 ,  H01L29/7827

摘要： A power semiconductor device includes a substrate, a main body, and an electrode unit. The main body includes an active portion disposed on the substrate, an edge termination portion, and an insulating layer disposed on the edge termination portion. The edge termination portion includes first-type semiconductor region, a second-type semiconductor region and a top surface. The first-type semiconductor region is adjacent to the active portion and has a first-type doping concentration decreased from the top surface toward the substrate. The electrode unit includes a first electrode disposed on the insulating layer, and a second electrode disposed on the substrate.

公开(公告)号：US09852979B2

公开(公告)日：2017-12-26

申请号：US15339550

申请日：2016-10-31

申请人： Texas Instruments Incorporated

发明人： Matthew D. Romig ,  Frank Stepniak ,  Saumya Gandhi

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L21/288 ,  H01L21/78 ,  H01L29/02 ,  H01L21/3105 ,  H05K1/18 ,  H05K1/11 ,  H05K1/16 ,  H01L49/02 ,  H01L23/00

CPC分类号： H01L23/5223 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/14 ,  H01L28/60 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H05K1/113 ,  H05K1/162 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/0187 ,  H05K2201/0215 ,  H05K2201/10734

摘要： An electronic system comprising an electronic body (301) with terminal pads (310) and at least one capacitor embedded in the electronic body. The capacitor including an insulating and adhesive first polymeric film (302) covering the body surface except the terminal pads; a sheet (320) of high-density capacitive elements, the first capacitor terminal being a metal foil (321) attached to film (302), the second terminal a conductive polymeric compound (324), and the insulator a dielectric skin (323). Sheet (320) has sets of via holes: the first set holes reaching metal foil 321), the second set holes reaching the terminals (310), and the third set holes reaching the conductive polymeric compound (324). An insulating second polymeric film (303) lining the sidewalls of the holes and planarizing the sheet surface; and metal (432) filling the via holes between the polymeric sidewalls and forming conductive traces and attachment pads on the system surface.