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    VERTICAL TRANSISTOR INCLUDING SYMMETRICAL SOURCE/DRAIN EXTENSION JUNCTIONS
    5.
    发明申请
    VERTICAL TRANSISTOR INCLUDING SYMMETRICAL SOURCE/DRAIN EXTENSION JUNCTIONS 有权

    公开(公告)号：US20220130980A1

    公开(公告)日：2022-04-28

    申请号：US17569669

    申请日：2022-01-06

    申请人： International Business Machines Corporation

    发明人： Chun-Chen Yeh ,  Alexander Reznicek ,  Veeraraghavan Basker ,  Junli Wang

    IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/223 ,  H01L29/06

    摘要： A semiconductor device includes a first source/drain region on an upper surface of a semiconductor substrate that extends along a first direction to define a length and a second direction opposite the first direction to define a width. A channel region extends vertically in a direction perpendicular to the first and second directions from a first end contacting the first source/drain region to an opposing second end contacting a second source/drain region. A gate surrounds a channel portion of the channel region, and a first doped source/drain extension region is located between the first source/drain region and the channel portion. The first doped source/drain extension region has a thickness extending along the vertical direction. A second doped source/drain extension region is located between the second source/drain region and the channel portion. The second doped source/drain extension region has a thickness extending along the vertical direction that matches the first thickness.

    VERTICAL FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED SOURCE AND DRAIN TOP JUNCTION
    6.
    发明申请
    VERTICAL FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED SOURCE AND DRAIN TOP JUNCTION 有权

    公开(公告)号：US20220059677A1

    公开(公告)日：2022-02-24

    申请号：US17453122

    申请日：2021-11-01

    申请人： International Business Machines Corporation

    发明人： Ruilong Xie ,  Chun-Chen Yeh ,  Alexander Reznicek ,  Chen Zhang

    IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/16 ,  H01L29/417 ,  H01L29/08

    摘要： A vertical field effect transistor includes a first epitaxial region in contact with a top surface of a channel fin extending vertically from a bottom source/drain located above a substrate, a second epitaxial region above the first epitaxial region having a horizontal thickness that is larger than a horizontal thickness of the first epitaxial region. The first epitaxial region and the second epitaxial region form a top source/drain region of the semiconductor structure. The first epitaxial region has a first doping concentration and the second epitaxial region has a second doping concentration that is lower than the first doping concentration. A top spacer, adjacent to the first epitaxial region and the second epitaxial region, is in contact with a top surface of a high-k metal gate stack located around the channel fin and in contact with a top surface of a first dielectric layer disposed between adjacent channel fins.

    Nanosheet device integrated with a FINFET transistor
    7.
    发明授权
    Nanosheet device integrated with a FINFET transistor 有权

    公开(公告)号：US11158636B2

    公开(公告)日：2021-10-26

    申请号：US16773337

    申请日：2020-01-27

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Chun-Chen Yeh ,  Ruilong Xie ,  Alexander Reznicek

    IPC分类号： H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49

    摘要： A semiconductor device includes a nanosheet device and a gate-all-around FIN-shaped (GAA-FIN) device. The nanosheet device includes n- and p-type field effect transistor (nFET and pFET) sections, each of which includes nanosheet stacks and work function metal (WFM). Each nanosheet stack includes lowermost and uppermost spacers, intermediate semiconductor layers and dielectric material surrounding the lowermost and uppermost spacers and the intermediate semiconductor layers. The WFM surrounds the nanosheet stacks and entirely fills suspension regions thereof. The GAA-FIN device includes nFET and pFET sections, each of which includes fin elements and WFM. Each fin element includes a lower spacer, a secondary intermediate layer of semiconductor material and dielectric material surrounding the lower spacer and the secondary intermediate layer of semiconductor material. The WFM surrounds each of the fin elements. A thickness of the WFM entirely filling the suspension regions exceeds a thickness of the WFM of the fin elements.