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公开(公告)号：US11990508B2
公开(公告)日：2024-05-21
申请号：US17405455
申请日：2021-08-18
CPC分类号： H01L29/0669 , H01L29/0653 , H01L29/16 , H01L29/66666 , H01L29/7827
摘要： Semiconductor devices and methods of forming the same include recessing sacrificial layers in a stack of alternating sacrificial layers and channel layers using a first etch to form curved recesses at sidewalls of each sacrificial layer in the stack, with tails of sacrificial material being present at a top and bottom of each curved recess. Dielectric plugs are formed that each partially fill a respective curved recess, leaving exposed at least a portion of each tail of sacrificial material. The tails of sacrificial material are etched back using a second etch to expand the recesses. Inner spacers are formed in the expanded recesses.
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公开(公告)号：US11955526B2
公开(公告)日：2024-04-09
申请号：US17304112
申请日：2021-06-15
IPC分类号： H01L27/12 , H01L21/02 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号： H01L29/42392 , H01L21/02532 , H01L21/0259 , H01L29/0665 , H01L29/66553 , H01L29/66742 , H01L29/78696 , H01L2029/42388
摘要： An apparatus comprising a substrate and a thin gate oxide nanosheet device located on the substrate, having a first plurality of nanosheet layers, wherein each of the first plurality of nanosheet layers has a first thickness located at the center of the nanosheet. A thick gate oxide nanosheet device located on the substrate, having a second plurality of nanosheet layers, wherein each of the second plurality of nanosheet layers has a second thickness and wherein the first thickness is less than the second thickness.
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公开(公告)号：US11894361B2
公开(公告)日：2024-02-06
申请号：US17545501
申请日：2021-12-08
发明人： Julien Frougier , Sagarika Mukesh , Anthony I. Chou , Andrew M. Greene , Ruilong Xie , Veeraraghavan S. Basker , Junli Wang , Effendi Leobandung , Jingyun Zhang , Nicolas Loubet
IPC分类号： H01L27/02 , H01L21/8234 , H01L21/84 , H01L27/12
CPC分类号： H01L27/0255 , H01L21/823481 , H01L21/84 , H01L27/0296 , H01L27/1207 , H01L27/1211
摘要： A semiconductor device is provided. The semiconductor device includes a first field effect device on a first region of a substrate, wherein a first gate structure and an electrostatic discharge device on a second region of the substrate, wherein a second gate structure for the electrostatic discharge device is separated from the substrate by the bottom dielectric layer, and a second source/drain for the electrostatic discharge device is in electrical contact with the substrate, wherein the second source/drain is doped with a second dopant type.
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公开(公告)号：US11695057B2
公开(公告)日：2023-07-04
申请号：US17346798
申请日：2021-06-14
发明人： Yao Yao , Ruilong Xie , Andrew Greene , Veeraraghavan S. Basker
IPC分类号： H01L29/66 , H01L21/306 , H01L29/08 , H01L29/40 , H01L21/311 , H01L21/308 , H01L29/10 , H01L29/06 , H01L29/78 , H01L21/02
CPC分类号： H01L29/66553 , H01L21/02532 , H01L21/3083 , H01L21/30604 , H01L21/31111 , H01L29/0673 , H01L29/0847 , H01L29/1037 , H01L29/401 , H01L29/6653 , H01L29/6656 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L21/0262
摘要： A method for manufacturing a semiconductor device includes forming a plurality of first semiconductor layers alternately stacked with a plurality of second semiconductor layers on a semiconductor substrate, and laterally recessing the plurality of first semiconductor layers with respect to the plurality of second semiconductor layers to form a plurality of vacant areas on lateral sides of the plurality of first semiconductor layers. In the method, a plurality of first inner spacers are formed on the lateral sides of the plurality of first semiconductor layers in respective ones of the plurality of vacant areas, and a plurality of second inner spacers are formed on sides of the plurality of first inner spacers in the respective ones of the plurality of vacant areas. The method also includes laterally recessing the plurality of second semiconductor layers, and growing a plurality of source/drain regions from the plurality of second semiconductor layers.
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公开(公告)号：US20230133545A1
公开(公告)日：2023-05-04
申请号：US17518515
申请日：2021-11-03
发明人： Julien Frougier , Nicolas Loubet , Andrew M. Greene , Ruilong Xie , Maruf Amin Bhuiyan , Veeraraghavan S. Basker
IPC分类号： H01L29/423 , H01L29/06 , H01L29/66
摘要： A semiconductor device includes a semiconductor substrate, a first pair of FET (field effect transistor) gate structures separated by a first gate canyon having a first gate canyon spacing, disposed upon the semiconductor substrate, a second pair of FET gate structures separated by a second gate canyon having a second gate canyon spacing, disposed upon the substrate, a first S/D (source/drain region disposed in the first gate canyon, a second S/D region disposed in the second gate canyon, a first BDI (bottom dielectric isolation) element disposed below the first S/D region and having a first BDI thickness, and a second BDI element disposed below the second S/D region and having a second BDI thickness. The first BDI thickness exceeds the second BDI thickness.
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公开(公告)号：US11621332B2
公开(公告)日：2023-04-04
申请号：US17148911
申请日：2021-01-14
IPC分类号： H01L29/417 , H01L23/535 , H01L29/786 , H01L29/423 , H01L29/40 , H01L21/8234 , H01L23/528
摘要： An approach to form a semiconductor structure with a buried power rail. The semiconductor structure includes a buried power rail in a semiconductor substrate where a buried contact contacts to a first portion of a top surface of the buried power rail to a source/drain of a semiconductor device. Additionally, the semiconductor structure includes a first portion of a top surface of the buried contact that is below a top surface of the source/drain of the semiconductor device and a portion of a bottom surface of the buried contact that is in a cavity formed in the source/drain of the semiconductor device.
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公开(公告)号：US11349029B2
公开(公告)日：2022-05-31
申请号：US16719240
申请日：2019-12-18
摘要： A semiconductor structure is provided that includes non-metal semiconductor alloy containing contact structures for field effect transistors (FETs), particularly p-type FETs. Notably, each non-metal semiconductor alloy containing contact structure includes a highly doped epitaxial semiconductor material directly contacting a topmost surface of a source/drain region of the FET, a titanium liner located on the highly doped epitaxial semiconductor material, a diffusion barrier liner located on the titanium liner, and a contact metal portion located on the diffusion barrier liner.
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公开(公告)号：US11348999B2
公开(公告)日：2022-05-31
申请号：US16817692
申请日：2020-03-13
IPC分类号： H01L29/06 , H01L29/78 , H01L29/417 , H01L21/02 , H01L29/66 , H01L29/786 , H01L29/423
摘要： A method of manufacturing a nanosheet field effect transistor (FET) device is provided. The method includes forming a plurality of nanosheet stacks on a substrate, the nanosheet stacks including alternating layers of sacrificial layers and active semiconductor layers. The method includes removing portions of the sacrificial layers to form angular indents in each side thereof, then filling the indents with a low-κ material layer. The method further includes forming source drain regions between the nanosheet stacks, removing remaining portions of the sacrificial layers, and then forming gate metal layers in spaces formed by the removal of the sacrificial layers.
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公开(公告)号：US11043451B2
公开(公告)日：2021-06-22
申请号：US16514333
申请日：2019-07-17
IPC分类号： H01L21/8234 , H01L23/525 , H01L23/522 , H01L23/532 , H01L49/02 , H01L23/535 , H01L27/06 , H01L21/3105 , H01L21/311 , H01C17/00 , H01H69/02 , H01L29/49 , H01L29/66
摘要： Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.
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公开(公告)号：US10957761B2
公开(公告)日：2021-03-23
申请号：US16365642
申请日：2019-03-26
摘要： Self-limiting cavities are formed within a crystalline semiconductor substrate and beneath a stack of semiconductor layers used to form a nanosheet transistor device. Inner ends of the cavities merge beneath the stack while the outer ends thereof adjoin isolation regions within the substrate. The cavities are filled with electrically insulating material to provide bottom device isolation. Source/drain regions are grown in vertical trenches extending through the stack of semiconductor layers following formation of dielectric inner spacers. The bottom ends of the trenches adjoin the electrically insulating material within the cavities.
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