公开(公告)号：US12087691B2

公开(公告)日：2024-09-10

申请号：US17480531

申请日：2021-09-21

申请人： International Business Machines Corporation

发明人： Ruilong Xie ,  Julien Frougier ,  Veeraraghavan S. Basker ,  Lawrence A. Clevenger ,  Nicolas Loubet ,  Dechao Guo ,  Kisik Choi ,  Kangguo Cheng ,  Carl Radens

IPC分类号： H01L27/088 ,  H01L21/768 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L23/5286 ,  H01L21/76895 ,  H01L27/0886 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/78696

摘要： A semiconductor structure comprises a substrate having a first side and a second side opposite the first side, and a gate for at least one transistor device disposed above the first side of the substrate. The structure may further include a buried power rail at least partially disposed in the substrate and a gate tie-down contact connecting the gate to the buried power rail from the second side of the substrate. The structure may further or alternatively include one or more source/drain regions disposed over the first side of the substrate, and a gate contact connecting to a portion of the gate from the second side of the substrate, the portion of the gate being adjacent to at least one of the one or more source/drain regions.

公开(公告)号：US20230124681A1

公开(公告)日：2023-04-20

申请号：US17504765

申请日：2021-10-19

申请人： International Business Machines Corporation

发明人： Ruilong Xie ,  Su Chen Fan ,  Veeraraghavan S. Basker ,  Julien Frougier ,  Nicolas Loubet

IPC分类号： H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/417

摘要： A CMOS (complementary metal-oxide semiconductor) device includes an n-channel metal-oxide semiconductor (NMOS) device, a p-channel metal-oxide semiconductor (PMOS) device, the NMOS and the PMOS device surrounded by a first dielectric material, the NMOS device separated from the PMOS device by a second dielectric material, a first NMOS gate separated from a first PMOS gate by the second dielectric material, a second NMOS gate electrically connected to a second PMOS gate by a metal link disposed between the NMOS gate and the PMOS gate, the metal link disposed above the second dielectric material, a first source/drain (S/D) contact disposed above the second dielectric material, the first S/D contact disposed in contact with both NMOS S/D region and a PMOS S/D region, and a second S/D contact disposed adjacent to the second dielectric material, the second S/D contact disposed in contact with a single S/D region.

公开(公告)号：US20230094466A1

公开(公告)日：2023-03-30

申请号：US17486840

申请日：2021-09-27

申请人： International Business Machines Corporation

发明人： Julien Frougier ,  Nicolas Loubet ,  Sagarika Mukesh ,  PRASAD BHOSALE ,  Ruilong Xie ,  Andrew Herbert Simon ,  Takeshi Nogami ,  Lawrence A. Clevenger ,  Roy R. Yu ,  Andrew M. Greene ,  Daniel Charles Edelstein

IPC分类号： H01L29/786 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

摘要： A semiconductor structure includes a substrate and a first field effect transistor (FET) formed on the substrate; the first FET includes a first FET first source-drain region, a first FET second source-drain region, a first FET gate between the first and second source-drain regions, and a first FET channel region adjacent the first FET gate and between the first FET first and second source-drain regions. Also included is a buried power rail, buried in the substrate, having a top at a level lower than the first FET channel region, and having buried power rail sidewalls. A first FET shared contact is electrically interconnected with the buried power rail and the first FET second source-drain region, and a first FET electrically isolating region is adjacent the buried power rail sidewalls and separates the buried power rail from the substrate.

公开(公告)号：US11605672B2

公开(公告)日：2023-03-14

申请号：US17128786

申请日：2020-12-21

申请人： International Business Machines Corporation

发明人： Julien Frougier ,  Nicolas Loubet ,  Ruilong Xie ,  Daniel Chanemougame ,  Ali Razavieh ,  Kangguo Cheng

IPC分类号： H01L27/24 ,  H01L45/00 ,  H01L29/78 ,  H01L21/3213

摘要： Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a trench extending to the source/drain. A trench contact is formed in the trench in contact with the source/drain. A recess is formed in a portion of the trench contact below a top surface of the cap using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch.

公开(公告)号：US20210257450A1

公开(公告)日：2021-08-19

申请号：US17240002

申请日：2021-04-26

申请人： International Business Machines Corporation ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Nicolas Loubet ,  Tenko Yamashita ,  Guillaume Audoit ,  Nicolas Bernier ,  Remi Coquand ,  Shay Reboh

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/417

摘要： Provided are embodiments for a semiconductor device. The semiconductor device includes a nanosheet stack comprising one or more layers, wherein the one or more layers are induced with strain from a modified sacrificial gate. The semiconductor device also includes one or more merged S/D regions formed on exposed portions of the nanosheet stack, wherein the one or more merged S/D regions fix the strain of the one or more layers, and a conductive gate formed over the nanosheet stack, wherein the conductive gate replaces a modified sacrificial gate without impacting the strain induced in the one or more layers. Also provided are embodiments for a method for creating stress in the channel of a nanosheet transistor.

公开(公告)号：US10991808B2

公开(公告)日：2021-04-27

申请号：US16733846

申请日：2020-01-03

申请人： International Business Machines Corporation

发明人： Julien Frougier ,  Nicolas Loubet ,  Ruilong Xie ,  Daniel Chanemougame ,  Ali Razavieh ,  Kangguo Cheng

IPC分类号： H01L23/525 ,  H01L29/43 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/3105 ,  H01L49/00 ,  H01L29/417 ,  H01L29/66 ,  H04L29/08 ,  H01L27/24 ,  H01L27/22

摘要： Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, a trench contact formed on and in contact with the source/drain, and a source/drain contact formed on an in contact with the trench contact. A recess is formed in a portion of the source/drain contact using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the source/drain contact. A metallization layer is formed in contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.

公开(公告)号：US10903369B2

公开(公告)日：2021-01-26

申请号：US16286733

申请日：2019-02-27

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ruilong Xie ,  Julien Frougier ,  Chanro Park ,  Edward Nowak ,  Yi Qi ,  Kangguo Cheng ,  Nicolas Loubet

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L21/30 ,  H01L29/423 ,  H01L21/225 ,  H01L21/762

摘要： Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a non-planar channel region is formed having a first semiconductor layer, a second semiconductor layer, and a fin-shaped bridge layer between the first semiconductor layer and the second semiconductor layer. Forming the non-planar channel region can include forming a nanosheet stack over a substrate, forming a trench by removing a portion of the nanosheet stack, and forming a third semiconductor layer in the trench. Outer surfaces of the first semiconductor layer, the second semiconductor layer, and the fin-shaped bridge region define an effective channel width of the non-planar channel region.

公开(公告)号：US20200312977A1

公开(公告)日：2020-10-01

申请号：US16363355

申请日：2019-03-25

申请人： International Business Machines Corporation

发明人： Nicolas Loubet ,  Kangguo Cheng ,  Wenyu Xu ,  Julien Frougier

IPC分类号： H01L29/49 ,  H01L29/66 ,  H01L29/78

摘要： Embodiments of the invention are directed to a method of fabricating a field effect transistor device, wherein the fabrication operations include forming a channel region over a substrate, forming a gate region over a top surface and along sidewalls of the channel region, and forming a source or drain (S/D) region over the substrate. A bottom encapsulated air-gap is formed over the substrate, and a first portion of the bottom encapsulated air-gap is positioned between the gate region and the S/D region. The first portion of the bottom encapsulated air-gap is further positioned below the top surface of the channel region.

公开(公告)号：US10714392B2

公开(公告)日：2020-07-14

申请号：US16038985

申请日：2018-07-18

申请人： International Business Machines Corporation ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Nicolas Loubet ,  Emmanuel Augendre ,  Remi Coquand ,  Shay Reboh

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088 ,  H01L21/3065 ,  H01L21/306

摘要： Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.

公开(公告)号：US10573755B1

公开(公告)日：2020-02-25

申请号：US16128869

申请日：2018-09-12

申请人： International Business Machines Corporation

发明人： Julien Frougier ,  Kangguo Cheng ,  Nicolas Loubet ,  Ruilong Xie

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L23/535 ,  H01L29/06 ,  H01L29/423 ,  H01L21/768

摘要： A method of fabricating a nanosheet semiconductor device includes depositing sacrificial material on a layer of silicon germanium (SiGe) above a substrate. A thickness of the sacrificial material is more than a thickness of the layer of SiGe. The method also includes forming nanosheet fins comprising alternating silicon (Si) nanosheets and silicon germanium (SiGe) layers on the sacrificial material, undercutting the SiGe layers to form divots, and forming a dummy gate structure above each of the nanosheet fins. A first liner is deposited to fill the divots and cover the nanosheet fins and the dummy gate structure. The sacrificial material and the first liner material are removed. The method also includes encapsulating the nanosheet fins and the dummy gate structure with a conformal liner, and performing an oxide fill to create a buried oxide (BOX) isolation between subsequently formed source and drain regions between the nanosheet fins and the substrate.