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公开(公告)号：US20230187531A1
公开(公告)日：2023-06-15
申请号：US17551402
申请日：2021-12-15
IPC分类号： H01L29/66 , H01L29/06 , H01L29/423 , H01L29/786 , H01L21/02
CPC分类号： H01L29/66545 , H01L21/0259 , H01L29/0665 , H01L29/42392 , H01L29/66553 , H01L29/66742 , H01L29/78696
摘要： A semiconductor device includes a first gate stack disposed over an active region and a second gate stack disposed over a shallow trench isolation (STI) region such that the first gate stack is taller than the second gate stack. The second gate stack includes a plurality of gates formed over a non-active region. The nanosheet stacks in the active region include first inner spacers and second inner spacers. The first inner spacers are vertically aligned with the second inner spacers. Further, the first inner spacers directly contact lower sidewalls of a source/drain epitaxial region to isolate the second gate stack from the STI region.
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公开(公告)号：US20230187342A1
公开(公告)日：2023-06-15
申请号：US17547669
申请日：2021-12-10
发明人： Nicholas Anthony Lanzillo , PRASAD BHOSALE , Alexander Edward Hess , SON NGUYEN , Rudy J. Wojtecki
IPC分类号： H01L23/522 , H01L21/768 , H01L21/3105
CPC分类号： H01L23/5226 , H01L21/76897 , H01L21/76879 , H01L21/31053 , H01L21/76883
摘要： A method of forming a fully-aligned via (FAV) structure is provided. The method includes arranging conductive material adjacent to a dielectric pad and chemically deactivating a surface of the conductive material by forming a dopant-free surface-aligned monolayer (SAM) thereon. Dielectric material is deposited onto the dielectric pad aside the dopant-free SAM and the dopant-free SAM is removed from the surface of the conductive material.
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公开(公告)号：US20230094466A1
公开(公告)日：2023-03-30
申请号：US17486840
申请日：2021-09-27
发明人： Julien Frougier , Nicolas Loubet , Sagarika Mukesh , PRASAD BHOSALE , Ruilong Xie , Andrew Herbert Simon , Takeshi Nogami , Lawrence A. Clevenger , Roy R. Yu , Andrew M. Greene , Daniel Charles Edelstein
IPC分类号： H01L29/786 , H01L23/528 , H01L29/06 , H01L29/423 , H01L29/66 , H01L21/8234
摘要： A semiconductor structure includes a substrate and a first field effect transistor (FET) formed on the substrate; the first FET includes a first FET first source-drain region, a first FET second source-drain region, a first FET gate between the first and second source-drain regions, and a first FET channel region adjacent the first FET gate and between the first FET first and second source-drain regions. Also included is a buried power rail, buried in the substrate, having a top at a level lower than the first FET channel region, and having buried power rail sidewalls. A first FET shared contact is electrically interconnected with the buried power rail and the first FET second source-drain region, and a first FET electrically isolating region is adjacent the buried power rail sidewalls and separates the buried power rail from the substrate.
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公开(公告)号：US20220407005A1
公开(公告)日：2022-12-22
申请号：US17353098
申请日：2021-06-21
发明人： Injo Ok , Nicole Saulnier , Kevin W. Brew , Steven Michael McDermott , Lawrence A. Clevenger , Hari Prasad Amanapu , ADRA CARR , PRASAD BHOSALE
IPC分类号： H01L45/00
摘要： A method for forming a phase-change memory cell includes depositing a metal layer over a wafer such that the metal layer covers connection structures of the wafer. The method further includes removing a portion of the metal layer such that the connection structures of the wafer remain covered by a remaining portion of the metal layer. The method further includes forming a phase-change memory stack on a stack area of the remaining portion of the metal layer. The method further includes removing the remaining portion of the metal layer except in the stack area.
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公开(公告)号：US20230238323A1
公开(公告)日：2023-07-27
申请号：US17585351
申请日：2022-01-26
发明人： Christopher J. Penny , Nicholas Anthony Lanzillo , Albert Chu , Ruilong Xie , Lawrence A. Clevenger , DANIEL JAMES DECHENE , Eric Miller , PRASAD BHOSALE
IPC分类号： H01L23/528 , H01L21/768
CPC分类号： H01L23/5286 , H01L23/5283 , H01L21/76802 , H01L21/76877
摘要： Interconnect structures including signal lines, power lines and ground lines are configured for improvements in routing and scaling. Vertical stacking of the relatively wide power and ground lines allows for additional signal tracks in the same footprint of a standard cell or other electronic device. Alternatively, vertical stacking of the signal lines allows an increased number of signal tracks. Such interconnect structures are formed during back-end-of-line processing using subtractive or damascene interconnect integration techniques.
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公开(公告)号：US20230178370A1
公开(公告)日：2023-06-08
申请号：US17542563
申请日：2021-12-06
IPC分类号： H01L21/027 , C23C16/04 , C23C16/56 , C23C16/02 , H01L21/02 , H01L21/768
CPC分类号： H01L21/0271 , C23C16/04 , C23C16/56 , C23C16/0227 , H01L21/02301 , H01L21/76829
摘要： Embodiments of the invention provide self-assembled monolayers (SAM) formulations and cleaning to promote quick depositions. A hydrogen-based plasma clean is performed on a structure, the structure including a metal layer and a dielectric layer. A self-assembled monolayers (SAM) solution is dispensed on the structure, the SAM solution including SAMs and a solvent, the SAMs being configured to assemble on the metal layer. The structure is rinsed with a rinse solution including the solvent.
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7.发明公开公开(公告)号：US20230142226A1
公开(公告)日：2023-05-11
申请号：US17522974
申请日：2021-11-10
发明人： Ruilong Xie , Nicolas Loubet , Julien Frougier , Lawrence A. Clevenger , PRASAD BHOSALE , Junli Wang , Balasubramanian Pranatharthiharan , Dechao Guo
IPC分类号： H01L27/06 , H01L27/092 , H01L29/423 , H01L21/822
CPC分类号： H01L27/0688 , H01L27/092 , H01L29/42392 , H01L21/8221
摘要： Embodiments of the invention include vertically stacked field-effect transistors (FETs). The vertically stacked FETs include at least one first transistor and at least one second transistor separated by a dielectric isolation layer. Gate material is adjacent to the at least one first transistor and the at least one second transistor, at least one first height vertical layer being adjacent to and about a height of the gate material, at least one second height vertical layer being adjacent to and less than the height of the gate material.
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