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公开(公告)号：US20240357822A1
公开(公告)日：2024-10-24
申请号：US18305653
申请日：2023-04-24
发明人： Min Gyu Sung , Julien Frougier , Ruilong Xie , Chanro Park , Juntao Li
IPC分类号： H10B43/35 , H01L23/528 , H01L25/065 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786 , H10B41/27 , H10B41/35 , H10B43/27 , H10B80/00
CPC分类号： H10B43/35 , H01L23/5283 , H01L25/0657 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78696 , H10B41/27 , H10B41/35 , H10B43/27 , H10B80/00
摘要： A memory device including a stack of nanostructures, a first plurality of nanosheets/nanowires from the stack of nanostructures having first source and drain regions at their opposing ends to position first channel regions for a first memory cell, and a second plurality of nanosheets/nanowires from the stack of nanostructures having second source and drain regions at their opposing ends to position second channel regions for a second memory cell. An isolation liner layer is present between the first source and drain regions and the second source and drain regions. The memory device further includes a shared gate all around (GAA) control gate for the first and second memory cell, the shared gate all around (GAA) control gate including tunnel dielectric layer on the first and second channel regions, a trap dielectric layer on the tunnel dielectric layer, and a control conductor on the trap dielectric layer.
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公开(公告)号：US12119341B2
公开(公告)日：2024-10-15
申请号：US17485961
申请日：2021-09-27
发明人： Huimei Zhou , Julien Frougier , Xuefeng Liu , Jingyun Zhang , Lan Yu , Heng Wu , Miaomiao Wang , Veeraraghavan S. Basker
IPC分类号： H01L27/02 , H01L21/02 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号： H01L27/0255 , H01L21/0259 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/092 , H01L29/0665 , H01L29/42392 , H01L29/66742 , H01L29/78618 , H01L29/78696
摘要： In one embodiment a semiconductor structure comprises a semiconductor substrate, a trench dielectric layer disposed in a trench of the semiconductor substrate, a first source/drain region disposed in contact with the semiconductor substrate, a gate and a second source/drain region. The gate is disposed between the first source/drain region and the second source/drain region. The semiconductor structure further comprises a dielectric isolation layer disposed between the semiconductor substrate and the second source/drain region.
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公开(公告)号：US12107014B2
公开(公告)日：2024-10-01
申请号：US17490266
申请日：2021-09-30
发明人： Julien Frougier , Huimei Zhou , Ruilong Xie , Chanro Park , Kangguo Cheng
IPC分类号： H01L29/775 , H01L21/8238 , H01L27/092 , H01L29/66
CPC分类号： H01L21/823807 , H01L21/823821 , H01L21/823842 , H01L21/82385 , H01L27/0924 , H01L29/66545
摘要： Semiconductor devices and methods of forming the same include a first device region, a second device region, and an inter-device dielectric spacer between the first device region and the second device region. The first device region includes a first device channel, a first-polarity work function metal layer on the first device channel, and a second-polarity work function metal layer on the first device channel. The second device region include a second device channel, and a second-polarity work function metal layer on the second device channel.
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公开(公告)号：US20240321645A1
公开(公告)日：2024-09-26
申请号：US18188496
申请日：2023-03-23
发明人： Juntao Li , Julien Frougier , Nicolas Jean Loubet , Chanro Park , Min Gyu Sung , Ruilong Xie
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L21/823475 , H01L21/823418 , H01L21/823481 , H01L27/088
摘要： A microelectronic device including a first nanosheet transistor includes a first source/drain and a second nanosheet transistor includes a second source/drain. The first source/drain and the second source/drain are adjacent to each other. Each of the first source/drain and the second source/drain have an asymmetrical profile when cut through the first and second source/drain.
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公开(公告)号：US20240321630A1
公开(公告)日：2024-09-26
申请号：US18187738
申请日：2023-03-22
发明人： Ruilong Xie , Christopher J. Waskiewicz , Chih-Chao Yang , Huai Huang , Koichi Motoyama , Julien Frougier
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/7682 , H01L21/76802 , H01L21/76834 , H01L21/76877 , H01L21/76897 , H01L23/5226 , H01L23/53252
摘要： A semiconductor structure including first metal lines embedded in a first dielectric layer, second metal lines embedded in a second dielectric layer, where the second metal lines arranged above the first metal lines, a top via extending between one of the first metal lines and one of the second metal lines, where the top via is self-aligned to the one of the first metal lines, and at least one air gap located adjacent to the top via between the first metal lines and the second metal lines.
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公开(公告)号：US20240313070A1
公开(公告)日：2024-09-19
申请号：US18183189
申请日：2023-03-14
发明人： Ruilong Xie , Chanro Park , Min Gyu Sung , Julien Frougier , Juntao Li
IPC分类号： H01L29/417 , H01L27/092 , H01L29/06 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L29/41733 , H01L27/0922 , H01L29/0673 , H01L29/66545 , H01L29/775 , H01L29/78696
摘要： A microelectronic device including a nanosheet transistor that includes a source/drain. At least a first and a second dielectric shoulders located on top of the source/drain and the at least the first and second dielectric shoulders are located at a permitter of the source/drain. The source/drain includes a gouged area located at a center of the source/drain. A source/drain contact connected to the source/drain, where the source/drain contact is in contact with a top surface the first dielectric shoulder. The source/drain contact includes a protrusion that extends into the source/drain, and the source/drain contact protrusion is located within the gouged area of the source/drain.
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公开(公告)号：US12087691B2
公开(公告)日：2024-09-10
申请号：US17480531
申请日：2021-09-21
发明人： Ruilong Xie , Julien Frougier , Veeraraghavan S. Basker , Lawrence A. Clevenger , Nicolas Loubet , Dechao Guo , Kisik Choi , Kangguo Cheng , Carl Radens
IPC分类号： H01L27/088 , H01L21/768 , H01L23/528 , H01L29/06 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/786
CPC分类号： H01L23/5286 , H01L21/76895 , H01L27/0886 , H01L29/0665 , H01L29/401 , H01L29/41775 , H01L29/42356 , H01L29/42392 , H01L29/78696
摘要： A semiconductor structure comprises a substrate having a first side and a second side opposite the first side, and a gate for at least one transistor device disposed above the first side of the substrate. The structure may further include a buried power rail at least partially disposed in the substrate and a gate tie-down contact connecting the gate to the buried power rail from the second side of the substrate. The structure may further or alternatively include one or more source/drain regions disposed over the first side of the substrate, and a gate contact connecting to a portion of the gate from the second side of the substrate, the portion of the gate being adjacent to at least one of the one or more source/drain regions.
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公开(公告)号：US12046643B2
公开(公告)日：2024-07-23
申请号：US17479966
申请日：2021-09-20
发明人： Julien Frougier , Ruilong Xie , Kangguo Cheng , Chanro Park
IPC分类号： H01L29/417 , H01L23/535 , H01L27/12 , H01L29/40 , H01L29/423 , H01L29/66
CPC分类号： H01L29/41733 , H01L23/535 , H01L27/1203 , H01L29/401 , H01L29/66742 , H01L29/42392
摘要： Semiconductor structures are disclosed which comprise semiconductor devices having buried power rails. In one example, a semiconductor structure comprises a plurality of semiconductor devices. Each of the semiconductor devices is isolated from an adjacent semiconductor device by a dielectric layer. The semiconductor structure further comprises a first diffusion break extending across the plurality of semiconductor devices, a second diffusion break extending across the plurality of semiconductor devices and a plurality of gates extending across the plurality of semiconductor devices. The gates are disposed between the first diffusion break and the second diffusion break. Each semiconductor device comprises a power rail extending between the first diffusion break and the second diffusion break under the plurality of gates.
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公开(公告)号：US20240222227A1
公开(公告)日：2024-07-04
申请号：US18089655
申请日：2022-12-28
发明人： Ruilong Xie , Julien Frougier , Min Gyu Sung , Chanro Park , Juntao Li
IPC分类号： H01L23/48 , H01L21/8234 , H01L29/06 , H01L29/417 , H01L29/786
CPC分类号： H01L23/481 , H01L21/823412 , H01L21/823418 , H01L21/823475 , H01L29/0673 , H01L29/41733 , H01L29/78696
摘要： Embodiments are disclosed for a semiconductor device and a method for fabrication. The device includes a first gate, having a top FET that is disposed above a bottom FET, and in electrical contact with a top source/drain epitaxial (S/D epi) and a back end of line (BEOL) interconnect. Additionally, the device includes the bottom FET. The bottom FET is in electrical contact with a bottom S/D epi. Further, a shallow backside contact is in electrical contact with the bottom S/D epi. Additionally, the device includes a deep via that is in electrical contact with the BEOL interconnect and the shallow backside contact. The deep via and the shallow backside contact provide a conductive path between the BEOL interconnect and the bottom S/D epi.
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公开(公告)号：US20240213338A1
公开(公告)日：2024-06-27
申请号：US18146988
申请日：2022-12-27
发明人： Tao Li , Kisik Choi , Nicolas Jean Loubet , Julien Frougier , Ruilong Xie
IPC分类号： H01L29/417 , H01L23/528 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/775
CPC分类号： H01L29/41766 , H01L23/5286 , H01L29/0673 , H01L29/401 , H01L29/41775 , H01L29/42392 , H01L29/775
摘要： A semiconductor device includes a transistor device, including a source and drain region, and a gate region. A bottom dielectric isolation layer is on a backside of the transistor device. A buffer layer is on a backside of the bottom dielectric isolation layer. A first conductive contact is positioned on a backside of the transistor device in contact with a backside of the source and drain region, through the bottom dielectric isolation layer and through the buffer layer. A second conductive contact is in contact with the gate region from a frontside of the gate region.
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