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公开(公告)号：US20240284687A1
公开(公告)日：2024-08-22
申请号：US18112020
申请日：2023-02-21
发明人： Min Gyu Sung , Julien Frougier , Ruilong Xie , Chanro Park , Juntao Li
IPC分类号： H10B99/00
摘要： A semiconductor structure includes an access transistor, a first memory device connected to a first side of the access transistor, and a second memory device connected to a second side of the access transistor. In some embodiments, the first memory device is connected to a first end of a first source/drain region of the access transistor and the second memory device is connected to a second end of the first source/drain region of the access transistor. In other embodiments, the first memory device is connected to a first source/drain region of the access transistor and the second memory device is connected to a second source/drain region of the access transistor.
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公开(公告)号：US20240188282A1
公开(公告)日：2024-06-06
申请号：US18060821
申请日：2022-12-01
发明人： Min Gyu Sung , Kangguo Cheng , Ruilong Xie , Chanro Park , Julien Frougier
CPC分类号： H01L27/10829 , H01L23/481 , H01L27/10814
摘要： A semiconductor structure having a high cell density is provided in which a frontside dynamic access memory (DRAM) is located on a frontside of a semiconductor substrate, and a backside DRAM is located on a backside of the semiconductor substrate. Peripheral transistors can be located on the frontside of the semiconductor substrate and at a same level as frontside transistors of the frontside DRAM.
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公开(公告)号：US12004435B2
公开(公告)日：2024-06-04
申请号：US17804912
申请日：2022-06-01
发明人： Min Gyu Sung , Soon-Cheon Seo , Chanro Park
CPC分类号： H10N70/8418 , H10B63/30 , H10N70/063 , H10N70/828 , H10N70/8833
摘要： A method of manufacturing an RRAM cell includes forming a first wire, forming an insulator on the first wire, the insulator having a pore and an insulator surface, and forming a first electrode layer on the first wire and the insulator, the first electrode having an electrode surface. The method further includes recessing the first electrode layer such that the electrode surface is recessed toward the first wire from the insulator surface, forming a switching layer on the insulator and the first electrode, and forming a second electrode on the switching layer.
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公开(公告)号：US20240145538A1
公开(公告)日：2024-05-02
申请号：US17974047
申请日：2022-10-26
发明人： Min Gyu Sung , Ruilong Xie , Chanro Park , Kangguo Cheng , Julien Frougier
IPC分类号： H01L29/06 , H01L23/48 , H01L27/092 , H01L29/08 , H01L29/786
CPC分类号： H01L29/0673 , H01L23/481 , H01L27/0924 , H01L29/0847 , H01L29/78696
摘要： A semiconductor structure comprises a source/drain region, a spacer layer on a first side of the source/drain region, a contact on a top surface of the source/drain region, and a via connected to a portion of the contact at a second side of the source/drain region, the second side of the source/drain region being opposite the first side of the source/drain region.
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公开(公告)号：US20240145472A1
公开(公告)日：2024-05-02
申请号：US17977281
申请日：2022-10-31
发明人： Kangguo Cheng , Julien Frougier , Ruilong Xie , Chanro Park , Min Gyu Sung
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823878 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775
摘要： A semiconductor structure includes a first transistor device, a second transistor device, and a dielectric pillar structure disposed between the first transistor device and the second transistor device. The dielectric pillar structure includes a first dielectric pillar adjacent the first transistor device and a second dielectric pillar adjacent the second transistor device.
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公开(公告)号：US20240130142A1
公开(公告)日：2024-04-18
申请号：US17967114
申请日：2022-10-17
发明人： Min Gyu Sung , Kangguo Cheng , Julien Frougier , Ruilong Xie , Chanro Park , Soon-Cheon Seo
IPC分类号： H01L27/24
CPC分类号： H01L27/2436 , H01L27/2463
摘要： A semiconductor structure comprises a first transistor, a second transistor vertically stacked over the first transistor, a source/drain region shared between the first transistor and the second transistor, and a resistive random-access memory device connected to the shared source/drain region.
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公开(公告)号：US20240120369A1
公开(公告)日：2024-04-11
申请号：US17961774
申请日：2022-10-07
发明人： Ruilong Xie , Julien Frougier , Kangguo Cheng , Chanro Park , Min Gyu Sung
IPC分类号： H01L49/02
CPC分类号： H01L28/91
摘要： A semiconductor structure includes a capacitor structure at least partially disposed in a trench of an interlayer dielectric layer. The capacitor structure includes first and second electrode layers separated by a dielectric layer. A top surface of the first electrode layer is below a top surface of the second electrode layer and the dielectric layer. A spacer is disposed on the first electrode layer and a contact is disposed in the trench and connected to the second electrode layer and the spacer.
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公开(公告)号：US20240096983A1
公开(公告)日：2024-03-21
申请号：US17932919
申请日：2022-09-16
发明人： Ruilong Xie , Kangguo Cheng , Julien Frougier , Chanro Park , Min Gyu Sung
IPC分类号： H01L29/417 , H01L23/528 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/40
CPC分类号： H01L29/41766 , H01L23/5286 , H01L27/092 , H01L29/0673 , H01L29/0847 , H01L29/401
摘要： A semiconductor structure having a backside contact structure with increased contact area includes a plurality of source/drain regions within a field effect transistor, each of the plurality of source/drain regions includes a top portion having an inverted V-shaped area. A backside power rail is electrically connected to at least one source/drain region through a backside metal contact. The backside metal contact wraps around a top portion of the at least one source/drain region. A tip of the top portion of the plurality of source/drain regions points towards the backside power rail with the top portion of the at least one source/drain region being in electric contact with the backside metal contact. A first epitaxial layer is in contact with a top portion of at least another source/drain region adjacent to the at least one source/drain region for electrically isolating the at least another source/drain region from the backside power rail.
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公开(公告)号：US20240038867A1
公开(公告)日：2024-02-01
申请号：US17877414
申请日：2022-07-29
发明人： Ruilong Xie , Julien Frougier , Kangguo Cheng , Chanro Park , Min Gyu Sung
IPC分类号： H01L29/423 , H01L29/06 , H01L27/092 , H01L21/8234
CPC分类号： H01L29/42392 , H01L29/0673 , H01L27/0922 , H01L21/823412
摘要： A microelectronic structure comprises a first stacked device structure comprising a first upper device and a first lower device, a second stacked device structure comprising a second upper device and a second lower device, and an isolation pillar structure located between the first and second stacked device structures. The isolation pillar structure has an upper section contacting the first and second upper devices and a lower section contacting the first and second lower devices. The upper section of the isolation pillar structure has a first width and the lower section of the isolation pillar structure has a second width different than the first width.
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10.发明公开公开(公告)号：US20230420457A1
公开(公告)日：2023-12-28
申请号：US17808360
申请日：2022-06-23
发明人： Julien Frougier , Andrew M. Greene , Shogo Mochizuki , Kangguo Cheng , Ruilong Xie , Heng Wu , Min Gyu Sung , Liqiao Qin , Gen Tsutsui
IPC分类号： H01L27/092 , H01L29/06 , H01L29/786 , H01L29/423 , H01L29/161 , H01L21/8238
CPC分类号： H01L27/0922 , H01L29/0665 , H01L21/823807 , H01L29/42392 , H01L29/161 , H01L29/78696
摘要： Embodiments of the invention include a single stack dual channel gate-all-around nanosheet with strained PFET and bottom dielectric isolation NFET. A PFET comprising at least one silicon germanium channel is formed. An NFET comprising at least one silicon channel is formed, the PFET being positioned laterally to the NFET, the at least one silicon channel and the at least one silicon germanium channel being staggered in a vertical direction.
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