公开(公告)号：US20250048677A1

公开(公告)日：2025-02-06

申请号：US18363889

申请日：2023-08-02

Applicant: International Business Machines Corporation

Inventor： Tao Li ,  Ruilong Xie ,  Tsung-Sheng Kang ,  Nicholas Alexander Polomoff ,  Huimei Zhou

IPC: H01L29/423 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes first nanosheet structures at an NFET region of a semiconductor substrate and second nanosheet structures at a PFET region. A first gate wraps around the first nanosheet structures and a second gate wraps around the second plurality of nanosheet structures. A dielectric bar is between the first nanosheet structures and the second nanosheet structures. The semiconductor device further includes a first backside contact in the NFET region and a second backside contact in the PFET region. The first backside contact includes a first backside contact extension that extends to a first side of the at least one dielectric bar. The second backside contact includes a second backside contact extension that extends to an opposing second side of the at least one dielectric bar. One or more backside power elements are on one or both of the first backside contact extension and the second contact extension.

公开(公告)号：US11804436B2

公开(公告)日：2023-10-31

申请号：US17466104

申请日：2021-09-03

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Huimei Zhou ,  Julien Frougier ,  Kisik Choi

IPC: H01L23/535 ,  H01L27/12 ,  H01L23/522 ,  H01L21/74

CPC classification number: H01L23/535 ,  H01L21/743 ,  H01L23/5226 ,  H01L27/1203

Abstract: A buried power rail is provided in a non-active device region. The buried power rail includes a dielectric liner located on a lower portion of a sidewall and a bottommost surface of the buried power rail. A dielectric cap is located on an upper portion of the sidewall of the buried power rail as well as on a topmost surface of the buried power rail. The dielectric cap is present during the fabrication of a functional gate structure and thus the problems associated with prior art buried power rails are circumvented. The dielectric cap can be removed after the functional gate structure has been formed and a via to buried power rail (VBPR) contact structure can be formed in contact with the buried power rail. In some applications, and after a gate cut process, a gate cut dielectric structure can be formed in contact with the dielectric cap.

公开(公告)号：US20230197813A1

公开(公告)日：2023-06-22

申请号：US17554394

申请日：2021-12-17

Applicant: International Business Machines Corporation

Inventor： Huimei Zhou ,  Ruilong Xie ,  Miaomiao Wang ,  Alexander Reznicek

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/0665 ,  H01L27/092 ,  H01L21/823828

Abstract: A semiconductor structure comprises a first nanosheet device having at least one first channel layer and a first gate, a second nanosheet device disposed above the first nanosheet device and having at least one second channel layer and a second gate, and an isolation layer disposed between the first nanosheet device and the second nanosheet device to electrically isolate the first nanosheet device and the second nanosheet device.

公开(公告)号：US20230102261A1

公开(公告)日：2023-03-30

申请号：US17485601

申请日：2021-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Andrew M. Greene ,  Julien Frougier ,  Ruqiang Bao ,  Jingyun Zhang ,  Miaomiao Wang ,  Dechao Guo

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/786

Abstract: Semiconductor devices, integrated chips, and methods of forming the same include forming a fill over a stack of semiconductor layers. The stack of semiconductor layers includes a first sacrificial layer and a set of alternating second sacrificial layers and channel layers. A dielectric fin is formed over the stack of semiconductor layers. The first sacrificial layer and the second sacrificial layers are etched away, leaving the channel layers supported by the dielectric fin over an exposed substrate surface. A dielectric layer is conformally deposited on the exposed substrate surface, the dielectric layer having a consistent thickness across the top surface. A conductive material is deposited over the dielectric layer.

公开(公告)号：US11282186B2

公开(公告)日：2022-03-22

申请号：US16822471

申请日：2020-03-18

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Liying Jiang ,  Derrick Liu ,  Jingyun Zhang ,  Huimei Zhou

IPC: G06T7/00 ,  G06N20/00 ,  G06K9/62 ,  G06V10/44 ,  G06K9/00 ,  G06F16/28

Abstract: An aspect of the invention includes reading a scale in image data representing an image of physical characteristics and resizing at least a portion of the image data to align with target image data representing a target image based at least in part on the scale to form resized image data representing one or more resized images. Noise reduction is applied to the resized image data to produce test image data representing one or more test images. A best fit analysis is performed on the test image data with respect to the target image data. Test image data having the best fit are stored with training image data representing classification training images indicative of one or more recognized features. An anomaly in unclassified image data representing an unclassified image is identified based at least in part on an anomaly detector as trained using the classification training images.

公开(公告)号：US11094781B2

公开(公告)日：2021-08-17

申请号：US16671609

申请日：2019-11-01

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Kangguo Cheng ,  Huimei Zhou ,  Ardasheir Rahman

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A nanosheet semiconductor structure and method for forming the same, where the nanosheet semiconductor structure includes a substrate and a nanosheet stack comprising vertically oriented nanosheets. A gate structure contacts and wraps around the vertically oriented nanosheets. A source layer and a drain layer are each disposed adjacent to the nanosheet stack. An inner spacer is disposed in contact with a bottom surface of the nanosheet stack. The method includes forming an alternating pattern of first spacers and second spacers on a semiconductor stack. The first spacers and one or more underlying portions of the semiconductor stack are removed thereby forming a plurality of trenches each adjacent to one or more of the second spacers. The plurality of trenches defines a plurality of vertically oriented nanosheets. A plurality of sacrificial spacers are formed each in contact with one or more vertically oriented nanosheets of the plurality of vertically oriented nanosheets.

公开(公告)号：US10665512B2

公开(公告)日：2020-05-26

申请号：US16163275

申请日：2018-10-17

Applicant: International Business Machines Corporation

Inventor： Huimei Zhou ,  Kangguo Cheng ,  Michael P. Belyansky ,  Oleg Gluschenkov ,  Richard A. Conti ,  James Kelly ,  Balasubramanian Pranatharthiharan

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/84 ,  H01L21/765 ,  H01L23/60 ,  H01L27/12 ,  H01L29/78

Abstract: Compressive and tensile stress is induced, respectively, on semiconductor fins in the pFET and nFET regions of a monolithic semiconductor structure including FinFETs. A tensile stressor is formed from dielectric material and a second, compressive stressor is formed from metal. The stressors may be formed in fin cut regions of the monolithic semiconductor structure and are configured to provide stress in the direction of FinFET current flow. The dielectric material may be deposited on the monolithic semiconductor structure and later removed from the fin cut regions of the pFET region. Metal exhibiting compressive residual stress is then deposited in the fin cut regions from which the dielectric material was removed. Gate cut regions may also be filled with the dielectric stressor material to impart substantially uniaxial tensile stress perpendicular to the semiconductor fins and perpendicular to electrical current flow.

公开(公告)号：US20200058555A1

公开(公告)日：2020-02-20

申请号：US16103433

申请日：2018-08-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Shogo Mochizuki ,  Gen Tsutsui ,  Ruqiang Bao

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02

Abstract: Integrated chips and methods of forming the same include etching a first stack of layers in a first region and etching a second stack of layers in a second region. The first stack of layers includes a first semiconductor layer having a first thickness over a first sacrificial layer having a second thickness. Etching the first stack of layers removes the first sacrificial layer from the first stack of layers and creates a first gap. The second stack of layers includes a second semiconductor layer having a third thickness over a second sacrificial layer having a fourth thickness. Etching the second stack of layers removes the second sacrificial layer from the second stack of layers and to create a second gap. A dielectric material fills the first gap and the second gap.

公开(公告)号：US10263098B2

公开(公告)日：2019-04-16

申请号：US15787768

申请日：2017-10-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Dechao Guo ,  Derrick Liu ,  Huimei Zhou

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/423 ,  H01L27/11 ,  H01L27/11529

Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.

公开(公告)号：US20180108661A1

公开(公告)日：2018-04-19

申请号：US15297863

申请日：2016-10-19

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Juntao Li ,  Sanjay C. Mehta ,  Robert R. Robison ,  Huimei Zhou

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L27/0924 ,  H01L21/02123 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/785

Abstract: A method of forming an improved field-effect transistor device is provided. The method includes forming a tensile stressor near a first semiconductor fin. The first semiconductor fin is a fin of an n-channel field-effect transistor. The n-channel field-effect transistor is formed on a substrate. The method also includes forming a compressive stressor near a second semiconductor fin. The second semiconductor fin is a fin of a p-channel field effect transistor. The p-channel field-effect transistor is formed on the substrate. The method can also include forming neutral material over the at least one n-channel and p-channel field effect transistor. The method can also include achieving different device performance by configuring a stressor distance to fin and/or by configuring a stressor volume.