公开(公告)号：US12237325B2

公开(公告)日：2025-02-25

申请号：US17136860

申请日：2020-12-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Su Chen Fan ,  Shogo Mochizuki ,  Peng Xu ,  Nicolas J. Loubet

IPC: H01L27/06 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H10B41/20 ,  H10B43/20 ,  H10B53/20 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/417

Abstract: A method of forming stacked vertical field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first spacer layer on the substrate, a first protective liner on the first spacer layer, a first gap layer on the first protective liner, a second protective liner on the first gap layer, a second spacer layer on the second protective liner, a sacrificial layer on the second spacer layer, a third spacer layer on the sacrificial layer, a third protective liner on the third spacer layer, a second gap layer on the third protective liner, a fourth protective liner on the second gap layer, and a fourth spacer layer on the fourth protective liner. The method further includes forming channels through the layer stack, a liner layer on the sidewalls of the channels, and a vertical pillar in the channels.

公开(公告)号：US20240421191A1

公开(公告)日：2024-12-19

申请号：US18335691

申请日：2023-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shogo Mochizuki ,  Erin Stuckert

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A transistor includes a funneled interfacial source/drain (S/D) region that includes a narrow throat that is connected to or is an interface to the nanolayer channel. The funneled interfacial S/D region may also include a wide throat that is an interface to a remainder of the S/D region. The funneled interfacial source/drain (S/D) region may reduce parasitic resistance or impedance from the S/D region into or out of a nanolayer channel.

公开(公告)号：US20240204100A1

公开(公告)日：2024-06-20

申请号：US18069077

申请日：2022-12-20

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Brent A. Anderson ,  Shogo Mochizuki ,  Lawrence A. Clevenger ,  Albert M. Chu ,  Nicholas Anthony Lanzillo

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/66666

Abstract: A semiconductor structure with self-aligned backside trench epitaxy includes a channel fin extending vertically from a bottom source/drain region of a field effect transistor. The bottom source/drain region includes a trench epitaxy later located underneath a bottommost surface of the channel fin. A high-k metal gate stack is disposed along sidewalls of the channel fin. The high-k metal gate is separated from the bottom source/drain region by a bottom spacer. A top source/drain region is located above a topmost surface of the channel fin. The top source/drain region is separated from the high-k metal gate by a top spacer. The semiconductor structure further includes a backside metal contact within a backside interlayer dielectric. The backside metal contact is electrically connected to, and vertically aligned with, the bottom source/drain region.

公开(公告)号：US20240178292A1

公开(公告)日：2024-05-30

申请号：US17994487

申请日：2022-11-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Indira Seshadri ,  Su Chen Fan ,  Jay William Strane ,  Stuart Sieg ,  Shogo Mochizuki

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/66553 ,  H01L29/775

Abstract: A semiconductor structure is presented including semiconductor layers of a first nanosheet stack, semiconductor layers of a second nanosheet stack formed over and having a stepped nanosheet formation with respect to the semiconductor layers of the first nanosheet stack, a first epitaxial growth formed adjacent the semiconductor layers of the first nanosheet stack, and a second epitaxial growth formed adjacent the semiconductor layers of the second nanosheet stack such that the second epitaxial growth has a stepped formation with respect to the first epitaxial growth. The second epitaxial growth has a volume greater than a volume of the first epitaxial growth.

公开(公告)号：US11996480B2

公开(公告)日：2024-05-28

申请号：US17470686

申请日：2021-09-09

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Shogo Mochizuki ,  Choonghyun Lee

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/66666

Abstract: VFET devices having symmetric, sharp channel-to-source/drain junctions and techniques for fabrication thereof using a late source/drain epitaxy process are provided. In one aspect, a VFET device includes: at least one vertical fin channel disposed on a substrate; a gate stack alongside the at least one vertical fin channel; a bottom source/drain region directly below the at least one vertical fin channel having, for example, an inverted T-shape with a flat bottom; and a top source/drain region over the at least one vertical fin channel. A method of fabricating a VFET device is also provided.

公开(公告)号：US20240145238A1

公开(公告)日：2024-05-02

申请号：US18050554

申请日：2022-10-28

Applicant: International Business Machines Corporation

Inventor： Reinaldo Vega ,  Shogo Mochizuki ,  Ruilong Xie ,  Julien Frougier ,  Ravikumar Ramachandran

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/0251 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775

Abstract: Embodiments of the invention include an isolation layer under a nanosheet stack of a transistor and a graded layer under the isolation layer. The graded layer includes an impurity gradient.

公开(公告)号：US20230420457A1

公开(公告)日：2023-12-28

申请号：US17808360

申请日：2022-06-23

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Andrew M. Greene ,  Shogo Mochizuki ,  Kangguo Cheng ,  Ruilong Xie ,  Heng Wu ,  Min Gyu Sung ,  Liqiao Qin ,  Gen Tsutsui

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L29/161 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L29/0665 ,  H01L21/823807 ,  H01L29/42392 ,  H01L29/161 ,  H01L29/78696

Abstract: Embodiments of the invention include a single stack dual channel gate-all-around nanosheet with strained PFET and bottom dielectric isolation NFET. A PFET comprising at least one silicon germanium channel is formed. An NFET comprising at least one silicon channel is formed, the PFET being positioned laterally to the NFET, the at least one silicon channel and the at least one silicon germanium channel being staggered in a vertical direction.

公开(公告)号：US20230402520A1

公开(公告)日：2023-12-14

申请号：US17806340

申请日：2022-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjay C. Mehta ,  Ruilong Xie ,  Shogo Mochizuki ,  Min Gyu Sung

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/417 ,  H01L21/822

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/41775 ,  H01L21/8221

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor device comprising: a bottom field effect transistor (FET); a top FET stacked over the bottom FET, where the top FET has a smaller active area than the bottom FET; a bottom gate formed in contact with the bottom FET; a top gate formed in contact with the top FET; and a bottom contact formed adjacent to the top gate, wherein an inner spacer is formed between the bottom contact and the top gate.

公开(公告)号：US11817502B2

公开(公告)日：2023-11-14

申请号：US17569133

申请日：2022-01-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Su Chen Fan ,  Shogo Mochizuki ,  Peng Xu ,  Nicolas J. Loubet

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L27/06 ,  H01L29/08

CPC classification number: H01L29/785 ,  H01L27/0688 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66795

Abstract: A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.

公开(公告)号：US20230282748A1

公开(公告)日：2023-09-07

申请号：US17653476

申请日：2022-03-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shogo Mochizuki ,  Su Chen Fan ,  Nicolas Jean Loubet ,  Xuan Liu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/28568 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Embodiments of present invention provide a semiconductor device. The semiconductor structure includes a plurality of nanosheet (NS) channel layers having a plurality of source/drain (S/D) regions on sidewalls thereof; and a continuous contact via being in direct contact with the plurality of S/D regions, wherein the continuous contact via has a substantially same horizontal distance to each of the plurality of NS channel layers. A method of manufacturing the same is also provided.