公开(公告)号：US20250063710A1

公开(公告)日：2025-02-20

申请号：US18449792

申请日：2023-08-15

Applicant: International Business Machines Corporation

Inventor： Min Gyu Sung ,  Julien Frougier ,  Ruilong Xie ,  Liqiao Qin

IPC: H10B10/00

Abstract: Embodiments of the invention include a semiconductor structure having a first transistor having first nanosheets as first channel regions, a second transistor having second nanosheets as second channel regions, and a third transistor having third nanosheets as third channel regions. The first, second, and third nanosheets are formed of nanosheet material, where the first nanosheets are fewer in number than the second nanosheets. The semiconductor structure includes first end portions formed of the nanosheet material between first inner spacers in the first transistor. The first end portions are opposite one another and discontinuous in the first transistor.

公开(公告)号：US20250040240A1

公开(公告)日：2025-01-30

申请号：US18361255

申请日：2023-07-28

Applicant: International Business Machines Corporation

Inventor： Shay Reboh ,  Julien Frougier ,  Leon Sigal ,  Ruilong Xie

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device including a stacked structure including first vertically stacked channel regions positioned over second vertically stacked channel regions. The first and second vertically stacked channel regions have a mid dielectric layer positioned therebetween. A structure is present having a first portion in electrical communication with the first vertically stacked channel regions and a second portion in electrical communication with the second vertically stacked channel regions. The semiconductor device also includes at least one two-component gate cut structure present adjacent to the gate all around structure. A first component of the two-component gate cut structure in positioned on one side of the mid dielectric layer adjacent to the first portion of the gate structure, and a second component of the two-component gate cut structure is positioned on a second side of the mid dielectric layer adjacent to the second portion of the gate structure.

公开(公告)号：US20250040115A1

公开(公告)日：2025-01-30

申请号：US18358981

申请日：2023-07-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Julien Frougier

IPC: H10B10/00 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Embodiments of present invention provide a static random-access-memory (SRAM). The SRAM includes a first and a second pull-down (PD) transistor having respectively a first and a fourth set of nanosheets of a first width; a first and a second pass-gate (PG) transistor having respectively a second and a fifth set of nanosheets of a second width; and a first and a second pull-up (PU) transistor having respectively a third and a sixth set of nanosheets of a third width, wherein the first width is wider than the second width, the second width is wider than the third width, the first set of nanosheets is substantially aligned with the second set of nanosheets at one side of the first and second sets of nanosheets, and the fourth set of nanosheets is substantially aligned with the fifth set of nanosheets at one side of the fourth and fifth sets of nanosheets.

公开(公告)号：US20250006788A1

公开(公告)日：2025-01-02

申请号：US18342821

申请日：2023-06-28

Applicant: International Business Machines Corporation

Inventor： Min Gyu Sung ,  Rishikesh Krishnan ,  Erin Stuckert ,  Nicolas Jean Loubet ,  Julien Frougier

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a plurality of first nanosheet fin structures located in a dense array region of a substrate. The semiconductor device further includes a plurality of first isolation trenches between adjacent first nanosheet fin structures of the plurality of first nanosheet fin structures. The plurality of first isolation trenches include: a first trench isolation layer, a protective liner formed on top of the first trench isolation layer, and a second trench isolation layer located above the protective liner. The protective liner separates the first trench isolation layer from the second trench isolation layer and the first trench isolation layer is more dense than the second trench isolation layer.

公开(公告)号：US20240429280A1

公开(公告)日：2024-12-26

申请号：US18339294

申请日：2023-06-22

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Julien Frougier ,  Min Gyu Sung ,  Chanro Park ,  Ruilong Xie

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Embodiments of the invention are directed to an integrated circuit (IC) that includes a channel that includes a nanosheet stack; an etch-stop isolation (ESI) region over the nanosheet stack; and a portion of a first type of gate element between the ESI region and the nanosheet stack. The ESI region is operable to prevent etching the portion of the first type of gate element that is between the ESI region and the nanosheet stack.

公开(公告)号：US12154985B2

公开(公告)日：2024-11-26

申请号：US18232640

申请日：2023-08-10

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Chen Zhang ,  Julien Frougier ,  Alexander Reznicek ,  Shogo Mochizuki

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: A uniform moon-shaped bottom spacer for a VTFET device is provided utilizing a replacement bottom spacer that is epitaxially grown above a bottom source/drain region. After filling a trench that is formed into a substrate with a dielectric fill material that also covers the replacement bottom spacer, the replacement bottom spacer is accessed, removed and then replaced with a moon-shaped bottom spacer.

公开(公告)号：US20240339509A1

公开(公告)日：2024-10-10

申请号：US18296397

申请日：2023-04-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Andrew Gaul ,  Andrew M. Greene ,  Julien Frougier

IPC: H01L29/417 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/41733 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first transistor having a first source/drain region and a second transistor having a second source/drain region; a first source/drain contact around the first source/drain region and a second source/drain contact around the second source/drain region; and a dielectric filler between the first source/drain contact and the second source/drain contact, wherein the dielectric filler has a first portion on top of a second portion, sidewalls of the first portion of the dielectric filler being linearly tapered to result in a width at a top of the first portion being larger than a width at a bottom of the first portion. A method of forming the same is also provided.

公开(公告)号：US12112782B2

公开(公告)日：2024-10-08

申请号：US17469350

申请日：2021-09-08

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Karthik Yogendra ,  Dimitri Houssameddine ,  Kangguo Cheng ,  Ruilong Xie

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: An approach for minimizing stack height and reducing resistance of an MRAM (Magnetoresistive random-access memory) is disclosed. The approach leverages an MRAM device with a T shape magnetic bottom electrode. The T shape magnetic bottom electrode can be made from a lower resistance metal such as cobalt. Furthermore, the method of creating the MRAM can include, depositing a low-k dielectric layer, forming bottom electrode via within the low-k dielectric layer, depositing bottom electrode metal liner on the bottom electrode via, depositing bottom electrode magnetic metal on the bottom electrode metal liner, planarizing the bottom electrode magnetic metal, depositing coupling layer and an MRAM stack on the bottom electrode magnetic metal, patterning and etching anisotropically the MRAM stack and depositing in-situ conformal dielectric layer and forming a top contact via on the MRAM stack.

公开(公告)号：US20240332296A1

公开(公告)日：2024-10-03

申请号：US18193595

申请日：2023-03-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Julien Frougier ,  Huimei Zhou ,  Alexander Reznicek

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a vertical insulator pillar extending from the substrate. A first stack of horizontal sheets of a first channel device is coupled to a lateral first side of the vertical insulator pillar and a second stack of horizontal sheets of a second channel device is coupled to a lateral second side of the vertical insulator pillar, opposite the first stack of horizontal sheets. A first gate stack is wrapped around the first stack of horizontal sheets. A second gate stack is wrapped around the second stack of horizontal sheets. A first gate extension is coupled to a center portion of the first gate stack and extending laterally away from the second gate stack and a second gate extension is coupled to a center portion of the second gate stack and extending laterally away from the first gate stack.

公开(公告)号：US12106969B2

公开(公告)日：2024-10-01

申请号：US17205037

申请日：2021-03-18

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Balasubramanian Pranatharthiharan ,  Mukta Ghate Farooq ,  Julien Frougier ,  Takeshi Nogami ,  Roy R. Yu ,  Kangguo Cheng

IPC: H01L21/306 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/30625 ,  H01L21/76224 ,  H01L21/76816 ,  H01L23/5286

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a first recess partially through a substrate from a first side of the substrate, forming a dielectric layer in the first recess, forming a second recess partially through the dielectric layer from the first side of the substrate, and forming a buried power rail (BPR) in the second recess of the dielectric layer. The method also includes thinning the substrate from a second side of the substrate to a level of the dielectric layer, the second side of the substrate being opposite to the first side of the substrate.