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    PLANAR DEVICES WITH CONSISTENT BASE DIELECTRIC
    2.
    发明申请
    PLANAR DEVICES WITH CONSISTENT BASE DIELECTRIC 有权

    公开(公告)号：US20230102261A1

    公开(公告)日：2023-03-30

    申请号：US17485601

    申请日：2021-09-27

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Huimei Zhou ,  Andrew M. Greene ,  Julien Frougier ,  Ruqiang Bao ,  Jingyun Zhang ,  Miaomiao Wang ,  Dechao Guo

    IPC分类号： H01L29/06 ,  H01L21/8234 ,  H01L29/786

    摘要： Semiconductor devices, integrated chips, and methods of forming the same include forming a fill over a stack of semiconductor layers. The stack of semiconductor layers includes a first sacrificial layer and a set of alternating second sacrificial layers and channel layers. A dielectric fin is formed over the stack of semiconductor layers. The first sacrificial layer and the second sacrificial layers are etched away, leaving the channel layers supported by the dielectric fin over an exposed substrate surface. A dielectric layer is conformally deposited on the exposed substrate surface, the dielectric layer having a consistent thickness across the top surface. A conductive material is deposited over the dielectric layer.

    Parasitic capacitance reducing contact structure in a finFET
    3.
    发明授权
    Parasitic capacitance reducing contact structure in a finFET 有权

    公开(公告)号：US10388769B2

    公开(公告)日：2019-08-20

    申请号：US15815626

    申请日：2017-11-16

    申请人： International Business Machines Corporation

    发明人： Miaomiao Wang ,  Tenko Yamashita ,  Chun-chen Yeh ,  Hui Zang

    IPC分类号： H01L29/08 ,  H01L29/66 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8234

    摘要： In a fin-Field Effect Transistor (finFET), a recess is created at a location of a fin, the fin being coupled to a gate of the finFET, the recess extending into a substrate interfacing with the gate. The recess is filled at least partially with a first conductive material. The first conductive material is insulated from the gate. The fin is replaced with a replacement structure. The replacement structure is electrically connected to the first conductive material using a second conductive material. The second conductive material is insulated from a first surface of the finFET. A first electrical contact structure is fabricated on the first surface. A second electrical contact structure is fabricated on a second surface of the finFET, the second surface being on a different spatial plane than the first surface.

    Resistance tunable fuse structure formed by embedded thin metal layers
    9.
    发明授权
    Resistance tunable fuse structure formed by embedded thin metal layers 有权

    公开(公告)号：US10957642B1

    公开(公告)日：2021-03-23

    申请号：US16576870

    申请日：2019-09-20

    申请人： International Business Machines Corporation

    发明人： Alexander Reznicek ,  Chih-Chao Yang ,  Miaomiao Wang ,  Donald Francis Canaperi

    IPC分类号： H01L23/525

    摘要： A semiconductor structure includes a resistance tunable fuse stack structure. A fabrication method for forming the same includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer. The method forms a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer, the layers are interleaved in a stack forming a fuse stack structure. First and second fuse electrical contacts are formed in the fuse stack structure vertically extending through the layers and contacting the first and second fuse conductive layers. Selection of various attributes of the fuse stack structure tunes a resistance of a fuse formed between the first and second fuse electrical contacts in the fuse stack structure.