公开(公告)号：US12131951B2

公开(公告)日：2024-10-29

申请号：US17452450

申请日：2021-10-27

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Chuxian Liao ,  Jie Liu ,  Jun He ,  Lixia Zhang ,  Zhan Ying

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/52 ,  H01L23/532 ,  H01L29/40

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L23/53228 ,  H01L24/94

摘要： Embodiments of the present disclosure propose a semiconductor packaging method and a semiconductor structure. The semiconductor packaging method includes: providing a substrate; forming a metal pad on the substrate, where there is a gap between a sidewall of the metal pad and the substrate; and connecting multiple metal pads on substrates to each other.

公开(公告)号：US12119299B2

公开(公告)日：2024-10-15

申请号：US17182447

申请日：2021-02-23

申请人： FUJI ELECTRIC CO., LTD.

发明人： Sho Nakagawa

IPC分类号： H01L23/52 ,  H01L21/66 ,  H01L21/768 ,  H01L23/522 ,  H01L23/525 ,  H01L29/866 ,  H03K17/74

CPC分类号： H01L23/5256 ,  H01L21/76895 ,  H01L22/14 ,  H01L22/32 ,  H01L23/5226 ,  H01L29/866 ,  H03K17/74

摘要： A method for manufacturing a semiconductor device includes: forming a trimming element inside or over a semiconductor substrate; forming an insulating film on the trimming element; forming, on the insulating film, a first wiring layer connected to one end of the trimming element via a first contact region penetrating the insulating film; forming, on the insulating film, a second wiring layer connected to another end of the trimming element via a second contact region penetrating the insulating film; trimming the trimming element; and examining an insulated state between the semiconductor substrate and either the first wiring layer or the second wiring layer after the trimming.

公开(公告)号：US12112878B2

公开(公告)日：2024-10-08

申请号：US17105677

申请日：2020-11-27

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： Hsiao-Tsung Yen ,  Ka-Un Chan

IPC分类号： H01F27/28 ,  H01L23/52 ,  H01L23/522

CPC分类号： H01F27/2804 ,  H01L23/5227

摘要： An asymmetric spiral inductor is provided. The asymmetric spiral inductor includes a first winding, a second winding and a third winding. The first winding has a first end and a second end and is implemented in the ultra-thick metal (UTM) layer of a semiconductor structure. The second winding, which has a third end and a fourth end, is implemented in the re-distribution layer of the semiconductor structure and has a first maximum trace width. The third winding, which has a fifth end and a sixth end, is implemented in the UTM layer of the semiconductor structure and has a second maximum trace width smaller than the first maximum trace width. The second and third ends are connected through a first through structure, the fourth and fifth ends are connected through a second through structure, and the first and sixth ends are the two ends of the asymmetric spiral inductor.

公开(公告)号：US12106033B2

公开(公告)日：2024-10-01

申请号：US18341545

申请日：2023-06-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheok-Kei Lei ,  Zhe-Wei Jiang ,  Chi-Yu Lu ,  Yi-Hsin Ko ,  Chi-Lin Liu ,  Hui-Zhong Zhuang

IPC分类号： G06F30/398 ,  G06F30/327 ,  G06F30/392 ,  H01L23/52 ,  H01L23/522

CPC分类号： G06F30/398 ,  G06F30/327 ,  G06F30/392 ,  H01L23/52 ,  H01L23/5222

摘要： The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

公开(公告)号：US12100697B2

公开(公告)日：2024-09-24

申请号：US17185499

申请日：2021-02-25

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chang-Yu Lin ,  Cheng-Hsuan Wu

IPC分类号： H01L23/48 ,  G02B6/42 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/52 ,  H01L25/16

CPC分类号： H01L25/167 ,  G02B6/4202 ,  H01L21/78 ,  H01L23/3107 ,  H01L24/24 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/214 ,  H01L2224/24146 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/83203

摘要： A semiconductor package structure and a method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first electronic device and a second electronic device. The first electronic device has an active surface and a lateral surface angled with the active surface, and the lateral surface includes a first portion and a second portion that is non-coplanar with the first portion. The second electronic device is disposed on the active surface of the first electronic device.

公开(公告)号：US12094811B2

公开(公告)日：2024-09-17

申请号：US16096618

申请日：2017-04-21

申请人： Kulicke and Soffa Industries, Inc.

发明人： Val Marinov

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/52 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/36

CPC分类号： H01L23/49838 ,  H01L21/4814 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/52 ,  H01L24/16 ,  H01L24/83 ,  H01L24/97 ,  H05K1/028 ,  H05K1/0393 ,  H05K1/189 ,  H05K3/361 ,  H01L2224/16225 ,  H01L2224/83851 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181

摘要： An apparatus includes a first substrate including one or more electrical connection features; and an assembly including: a second substrate; conductive features formed on the second substrate, one or more of which are electrically connected to corresponding electrical connection features of the first substrate; and an electronic component between the second substrate and the first substrate and electrically connected to one or more of the conductive features.

公开(公告)号：US12074127B2

公开(公告)日：2024-08-27

申请号：US18059148

申请日：2022-11-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/482 ,  H01L23/485 ,  H01L23/498 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L24/05 ,  H01L23/48 ,  H01L23/481 ,  H01L23/482 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/52 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/26 ,  H01L24/28 ,  H01L24/29 ,  H01L23/53228 ,  H01L2224/0225 ,  H01L2224/0226 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13018 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/19041 ,  H01L2924/35121 ,  H01L2224/13 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05171 ,  H01L2924/00014 ,  H01L2224/05184 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2224/05147 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2224/05171 ,  H01L2924/01029 ,  H01L2924/013

摘要： A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.

公开(公告)号：US12068237B2

公开(公告)日：2024-08-20

申请号：US18051151

申请日：2022-10-31

申请人： Allegro MicroSystems, LLC

发明人： Sundar Chetlur ,  Maxim Klebanov ,  Cory Voisine ,  Kenneth Snowdon ,  Hsuan-Jung Wu

IPC分类号： H01L23/52 ,  H01L21/8234 ,  H01L23/522

CPC分类号： H01L23/5222 ,  H01L21/823493

摘要： An apparatus including; a substrate; an isolator that is formed over the substrate, the isolator including a silicon shield layer that is formed between a first buried oxide (BOX) layer and a second BOX layer; a silicon layer having an oxide trench structure formed therein, the oxide trench structure being arranged to define a first silicon island and a second silicon island; a first electronic circuit that is formed over the first silicon island; and a second electronic circuit that is formed over the second silicon island, the first electronic circuit being electrically coupled to the first electronic circuit.

公开(公告)号：US12057357B2

公开(公告)日：2024-08-06

申请号：US17212417

申请日：2021-03-25

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kyong Hwan Koh ,  Jongwan Kim ,  Juhyeon Oh ,  Yongkwan Lee

IPC分类号： H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/52 ,  H01L23/00

CPC分类号： H01L23/13 ,  H01L21/4803 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49838 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/06135 ,  H01L2224/48227 ,  H01L2224/49173 ,  H01L2224/73265

摘要： A semiconductor package includes a base substrate that includes a first surface and a second surface that face each other, a plurality of first metal line patterns disposed on the first surface, a plurality of second metal line patterns disposed on the second surface, a plurality of vias that penetrate the base substrate and connect the first metal line patterns to the second metal line patterns, a semiconductor chip disposed on the first surface, and a molding member that covers the first surface and the semiconductor chip. The base substrate includes at least one recess at a corner of the base substrate. The recess extends from the first surface toward the second surface. The molding member includes a protrusion that fills the recess.

公开(公告)号：US12040319B2

公开(公告)日：2024-07-16

申请号：US17356323

申请日：2021-06-23

申请人： Samsung Display Co., Ltd.

发明人： Jin Woo Lee ,  Zu Seok Oh ,  Da Sol Jeong ,  Kyung Ah Choi ,  Kyu Ri Hwang

IPC分类号： H01L25/16 ,  H01L23/48 ,  H01L23/52 ,  H01L23/535 ,  H01L27/12 ,  H01L33/60 ,  H01L33/62 ,  G09G3/22 ,  H01L33/44

CPC分类号： H01L25/167 ,  H01L23/481 ,  H01L23/52 ,  H01L23/535 ,  H01L27/124 ,  H01L33/60 ,  H01L33/62 ,  G09G3/22 ,  H01L33/44

摘要： A display device is provided. The display device includes: a substrate; a first electrode located on the substrate; a second electrode located between the substrate and the first electrode; a first light emitting element located on the same layer as the first electrode; and a contact electrode located on the first light emitting element, wherein one end of the first light emitting element contacts the first electrode, and the other end of the first light emitting element contacts the contact electrode.