公开(公告)号：US12131908B2

公开(公告)日：2024-10-29

申请号：US18383158

申请日：2023-10-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jar-Ming Ho

IPC: H10B12/00 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/532 ,  H01L23/544

CPC classification number: H01L21/28506 ,  H01L21/3213 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/544 ,  H10B12/00 ,  H10B12/09 ,  H10B12/50

Abstract: The present disclosure provides a semiconductor structure, which includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a plurality of first conductive plugs penetrating through the dielectric layer; a plurality of spacers surrounding the respective first conductive plugs; a lining layer covering the dielectric layer, the spacer and the first conductive plugs, wherein the lining layer and the first conductive plugs include manganese (Mn); a second conductive plug penetrating through the lining layer; and a second conductive layer over the lining layer and the second conductive plug.

公开(公告)号：US12113099B2

公开(公告)日：2024-10-08

申请号：US18359023

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Fu-Chiang Kuo

IPC: H01G4/35 ,  H01L23/532 ,  H01L49/02 ,  H01L21/285 ,  H01L29/94

CPC classification number: H01L28/60 ,  H01G4/35 ,  H01L21/2855 ,  H01L23/5329 ,  H01L28/91 ,  H01L29/945

Abstract: A deep trench is formed in a substrate. A layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers is formed over the substrate. The layer stack continuously extends into the deep trench, and a cavity is present in an unfilled volume of the deep trench. A dielectric fill material layer including a dielectric fill material is formed in the cavity and over the substrate. The dielectric fill material layer encapsulates a void that is free of any solid phase and is formed within a volume of the cavity. The void may expand or shrink under stress during subsequently handling of a deep trench capacitor including the layer stack to absorb mechanical stress and to increase mechanical stability of the deep trench capacitor.

公开(公告)号：US12094823B2

公开(公告)日：2024-09-17

申请号：US17314294

申请日：2021-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Hao Liao ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Chung-Ju Lee

IPC: H01L23/532 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L23/5329 ,  H01L21/7682 ,  H01L21/76885 ,  H01L29/41791 ,  H01L29/7851

Abstract: An interconnection structure, along with methods of forming such, are described. The interconnection structure includes a first portion of a conductive layer, a second portion of the conductive layer disposed adjacent the first portion of the conductive layer, and a dielectric foam disposed between the first and second portions of the conductive layer. The dielectric foam includes fluid gaps filled with carbon dioxide gas.

公开(公告)号：US20240304696A1

公开(公告)日：2024-09-12

申请号：US18119953

申请日：2023-03-10

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： TSE-YAO HUANG

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/29 ,  H01L23/31 ,  H01L23/532 ,  H01L29/40

CPC classification number: H01L29/49 ,  H01L21/28035 ,  H01L21/28061 ,  H01L21/2807 ,  H01L21/28525 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/3178 ,  H01L23/53271 ,  H01L23/5329 ,  H01L29/401 ,  H01L29/4916 ,  H01L29/4941 ,  H01L21/76802 ,  H01L23/53276 ,  H01L29/4236

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a capping mask layer positioned on the substrate; a first gate insulating layer positioned along the capping mask layer, inwardly positioned in the substrate, and including a U-shaped cross-sectional profile; a first work function layer positioned on the first gate insulating layer; a first conductive layer positioned on the first work function layer; and a first capping layer positioned on the first conductive layer. The first capping layer includes germanium oxide. A top surface of the first capping layer and a top surface of the capping mask layer are substantially coplanar.

公开(公告)号：US12080640B2

公开(公告)日：2024-09-03

申请号：US17475995

申请日：2021-09-15

Applicant: International Business Machines Corporation

Inventor： Tao Li ,  Ruilong Xie ,  Tsung-Sheng Kang ,  Alexander Reznicek

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/53257 ,  H01L23/5329

Abstract: Interconnect structures having top vias self-aligned to metal line ends and techniques for formation thereof are provided. In one aspect, an interconnect structure includes: at least one metal line disposed on a substrate; at least one top via over the at least one metal line, wherein the at least one top via is aligned with an end of the at least one metal line, and wherein a sidewall of the at least one top via is curved. A dielectric fill material can be disposed adjacent to the at least one top via having sidewalls that are also curved. A method of fabricating an interconnect structure is also provided.

公开(公告)号：US20240290723A1

公开(公告)日：2024-08-29

申请号：US18114120

申请日：2023-02-24

Applicant: Intel Corporation

Inventor： Jason Gamba ,  Suddhasattwa Nad ,  Sanjay Tharmarajah ,  Rajeev Ranjan ,  Greg Aponte

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5384 ,  H01L21/76834 ,  H01L21/76846 ,  H01L23/5329

Abstract: An apparatus comprises a first layer comprising a first dielectric material, and first and second regions on a first side of the first layer. The first regions comprise a first surface in a first plane, and each of the second regions comprise a second surface in a second plane spaced away from the first plane by a first distance. Sidewalls extend between the first surface and the second surfaces. The apparatus further comprises a plurality of conductive features, each conductive feature comprising a bottom surface on one of the second surfaces, and a barrier film comprising a second dielectric material that contacts the sidewalls.

公开(公告)号：US12057492B2

公开(公告)日：2024-08-06

申请号：US18367292

申请日：2023-09-12

Applicant: Intel Corporation

Inventor： Tahir Ghani ,  Byron Ho ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H10N70/00 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H10B10/00 ,  H10B63/00 ,  H10N70/20 ,  H01L23/00

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.

公开(公告)号：US20240258391A1

公开(公告)日：2024-08-01

申请号：US18323323

申请日：2023-05-24

Applicant: SK hynix Inc.

Inventor： Rho Gyu KWAK ,  In Su PARK ,  Jung Shik JANG ,  Jung Dal CHOI ,  Seok Min CHOI ,  Won Geun CHOI

IPC: H01L29/423 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L29/42356 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/5329

Abstract: A semiconductor device according to an embodiment of the present disclosure includes a first cell area and a second cell area adjacent to each other in a first direction, a support disposed between the first cell area and the second cell area, first gate lines stacked in the first cell area, first pads configured to extend from the first gate lines and configured to protrude upward along a first sidewall of the support, second gate lines stacked in the second cell area, second pads configured to extend from the second gate lines and configured to protrude upward along a second sidewall of the support, and first connection pads configured to extend in the first direction along a third sidewall of the support and configured to electrically connect the first pads with the second pads.

公开(公告)号：US20240250030A1

公开(公告)日：2024-07-25

申请号：US18100570

申请日：2023-01-23

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin CHANG CHIEN ,  Yuan-Chun TAI ,  Chiu-Wen LEE ,  Yu-Hsun CHANG ,  Tai-Yuan HUANG

IPC: H01L23/532 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/5329 ,  H01L23/31 ,  H01L23/49816 ,  H01L28/10

Abstract: An electronic device is provided. The electronic device includes an inductor and a dielectric layer. The inductor includes a first magnetic layer, a conductive trace over the first magnetic layer, and a second magnetic layer over the conductive trace. The dielectric layer includes a first portion between the second magnetic layer and an inclined surface of the first magnetic layer. A substantially constant distance between the second magnetic layer and the inclined surface of the first magnetic layer is defined by the dielectric layer.

公开(公告)号：US20240234206A1

公开(公告)日：2024-07-11

申请号：US18451808

申请日：2023-08-17

Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY

Inventor： Axel SCHERER

IPC: H01L21/768 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/20 ,  H01L21/311 ,  H01L23/532

CPC classification number: H01L21/76879 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/2059 ,  H01L21/31144 ,  H01L23/5329

Abstract: Methods for utilizing irradiation to selectively transform insulating self-developing resists, such as metal fluorides, into electrically conductive metals are described. The disclosed methods enable the fabrication of electrical components and structures with critical dimensions below 5 nanometers. Selective irradiation induces the conversion of insulating metal fluoride compounds into metals in predefined regions. Examples of applications include miniature wiring, quantum point contacts, miniature electroplating and via-holes fabrication by using fluoride as etching mask.