公开(公告)号：US20180337130A1

公开(公告)日：2018-11-22

申请号：US15596956

申请日：2017-05-16

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chien Lin CHANG CHIEN ,  Chin-Li KAO ,  Shih-Yu WANG ,  Chang Chi LEE

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L21/683

CPC分类号： H01L23/5384 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L2221/68345 ,  H01L2221/68359

摘要： A semiconductor package device includes a first interconnection structure, a non-silicon interposer and a first die. The first interconnection structure has a first pitch. The non-silicon interposer surrounds the first interconnection structure. The non-silicon interposer includes a second interconnection structure having a second pitch. The second pitch is larger than the first pitch. The first die is above the first interconnection structure and is electrically connected to the first interconnection structure.

公开(公告)号：US20240250030A1

公开(公告)日：2024-07-25

申请号：US18100570

申请日：2023-01-23

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chien Lin CHANG CHIEN ,  Yuan-Chun TAI ,  Chiu-Wen LEE ,  Yu-Hsun CHANG ,  Tai-Yuan HUANG

IPC分类号： H01L23/532 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L23/5329 ,  H01L23/31 ,  H01L23/49816 ,  H01L28/10

摘要： An electronic device is provided. The electronic device includes an inductor and a dielectric layer. The inductor includes a first magnetic layer, a conductive trace over the first magnetic layer, and a second magnetic layer over the conductive trace. The dielectric layer includes a first portion between the second magnetic layer and an inclined surface of the first magnetic layer. A substantially constant distance between the second magnetic layer and the inclined surface of the first magnetic layer is defined by the dielectric layer.

公开(公告)号：US20240155758A1

公开(公告)日：2024-05-09

申请号：US17981338

申请日：2022-11-04

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chien Lin CHANG CHIEN ,  Yuan-Chun TAI ,  Yu Hsin CHANG CHIEN ,  Chiu-Wen LEE ,  Chang Chi LEE

IPC分类号： H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC分类号： H05K1/0271 ,  H05K1/11 ,  H05K1/182 ,  H05K2201/068 ,  H05K2201/1003

摘要： An electronic device is provided. The electronic device includes a first dielectric layer, an electronic element, an encapsulant, and a second dielectric layer. The first dielectric layer has a first coefficient of thermal expansion (CTE). The electronic element is disposed over the first dielectric layer. The encapsulant encapsulates the electronic element and has a second CTE. The second dielectric layer is disposed over the encapsulant and having a third CTE. The second CTE ranges between the first CTE and the third CTE.

公开(公告)号：US20210265231A1

公开(公告)日：2021-08-26

申请号：US16799751

申请日：2020-02-24

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chien Lin CHANG CHIEN ,  Chiu-Wen LEE ,  Hung-Jung TU ,  Chang Chi LEE ,  Chin-Li KAO

IPC分类号： H01L23/367 ,  H01L23/48 ,  H01L23/00 ,  H01L21/48

摘要： The present disclosure provides a semiconductor device package. The semiconductor device package includes a first die, a second die, and a thermal dissipation element. The first die has a first surface. The second die is disposed on the first surface. The thermal dissipation element is disposed on the first surface. The thermal dissipation element includes a first portion extending in a first direction substantially parallel to the first surface and partially covered by the second die and a second portion extending in a second direction substantially perpendicular to the first surface to be adjacent to an edge of the second die.

公开(公告)号：US20170263589A1

公开(公告)日：2017-09-14

申请号：US15416907

申请日：2017-01-26

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chien Lin CHANG CHIEN ,  Chang Chi LEE ,  Chin-Li KAO ,  Dao-Long CHEN ,  Ta-Chien CHENG

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L21/78 ,  H01L23/31 ,  H01L23/367

CPC分类号： H01L25/0657 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3672 ,  H01L24/33 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06589

摘要： A semiconductor device package includes a package substrate, a first electronic device, a second electronic device and a first molding layer. The package substrate includes a first surface, a second surface opposite to the first surface, and an edge. The first electronic device is positioned over and electrically connected to the package substrate through the first surface. The second electronic device is positioned over and electrically connected to the first electronic device. The first molding layer is positioned over the package substrate, and the first molding layer encapsulates a portion of the first surface and the edge of the package substrate.

公开(公告)号：US20210265273A1

公开(公告)日：2021-08-26

申请号：US16798152

申请日：2020-02-21

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chien Lin CHANG CHIEN ,  Chiu-Wen LEE ,  Ian HU ,  Chang Chi LEE

IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L21/48

摘要： A semiconductor device package includes a plurality of semiconductor chips and an interposer structure. The interposer structure has a plurality of tiers for accommodating the plurality of semiconductor chips. The interposer structure includes at least one conductive via connecting to a pad of the plurality of semiconductor chips.

公开(公告)号：US20180158766A1

公开(公告)日：2018-06-07

申请号：US15884197

申请日：2018-01-30

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chien Lin CHANG CHIEN ,  Chin-Li KAO ,  Chang Chi LEE ,  Chih-Pin HUNG

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48

摘要： A method of manufacturing a semiconductor package includes: (a) providing a carrier; (b) disposing a dielectric layer and a conductive pad on the carrier; (c) disposing a redistribution layer on the dielectric layer to electrically connect to the conductive pad; (d) connecting a die to the redistribution layer; (e) removing at least a portion of the carrier to expose the conductive pad; and (f) disposing an electrical contact to electrically connect to the conductive pad.

公开(公告)号：US20170207153A1

公开(公告)日：2017-07-20

申请号：US15479074

申请日：2017-04-04

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chien Lin CHANG CHIEN ,  Chin-Li KAO ,  Chang Chi LEE ,  Chih-Pin HUNG

IPC分类号： H01L23/498 ,  H01L25/00 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L23/49816 ,  H01L21/4853 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06586

摘要： In one or more embodiments, a semiconductor package includes a redistribution layer, a conductive pad, a dielectric layer, a silicon layer, and a conductive contact. The redistribution layer includes a first surface and a second surface opposite to the first surface. The conductive pad is on the first surface of the redistribution layer. The dielectric layer is disposed on the first surface of the redistribution layer to cover a first portion of the conductive pad and to expose a second portion of the conductive pad. The silicon layer is disposed on the dielectric layer, the silicon layer having a recess to expose the second portion of the conductive pad. The conductive contact is disposed over the silicon layer and extends into the recess of the silicon layer.