Patent search ap:("Advanced Semiconductor Engineering Page Inc.") AND inv:"Dao-Long CHEN"

1.

发明申请
SEMICONDUCTOR DEVICE PACKAGE HAVING AN UNDERFILL BARRIER 审中-公开

公开(公告)号：US20180358238A1

公开(公告)日：2018-12-13

申请号：US15619415

申请日：2017-06-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Jin-Yuan LAI , Tang-Yuan CHEN , Ying-Xu LU , Dao-Long CHEN , Kwang-Lung LIN , Chih-Pin HUNG , Tse-Chuan CHOU , Ming-Hung CHEN , Chi-Hung PAN

IPC: H01L21/56 , H01L23/00 , H01L21/48 , H01L23/498

CPC classification number: H01L21/563 , H01L21/481 , H01L23/49838 , H01L23/49894 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/83 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/83143 , H01L2224/83493 , H01L2224/83888 , H01L2224/83889 , H01L2924/01006

Abstract: The present disclosure relates to a semiconductor device package comprising a substrate, a semiconductor device, and a underfill. The substrate includes a top surface defining a mounting area, and a barrier section on the top surface and adjacent to the mounting area. The semiconductor device is mounted on the mounting area of the substrate. The underfill is disposed between the semiconductor device and the mounting area and the barrier section of the substrate. A contact angle between a surface of the underfill and the barrier section is greater than or equal to about 90 degrees.

2.

发明申请
SEMICONDUCTOR DEVICES AND SEMICONDUCTOR PACKAGES 审中-公开

公开(公告)号：US20170278814A1

公开(公告)日：2017-09-28

申请号：US15076831

申请日：2016-03-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin HUNG , Dao-Long CHEN , Ying-Ta CHIU , Ping-Feng YANG

IPC: H01L23/00

CPC classification number: H01L24/13 , H01L24/05 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/1161 , H01L2224/11622 , H01L2224/13012 , H01L2224/13015 , H01L2224/13017 , H01L2224/13018 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/16145 , H01L2224/16227 , H01L2224/81385 , H01L2224/81815 , H01L2924/00012 , H01L2924/014 , H01L2924/00014

Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.

3.

发明申请
SUBSTRATE AND SEMICONDUCTOR DEVICE PACKAGE 审中-公开

公开(公告)号：US20190080993A1

公开(公告)日：2019-03-14

申请号：US15702700

申请日：2017-09-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Dao-Long CHEN , Chih-Pin HUNG

IPC: H01L23/498 , H01L23/29

Abstract: A substrate including a dielectric layer and a patterned conductive layer adjacent to the dielectric layer is provided. The patterned conductive layer comprises a first conductive pad, the first conductive pad comprises a first portion having a first concave sidewall. The substrate further includes a protection layer disposed on the patterned conductive layer, and the protection layer covers the first portion of the first conductive pad.

4.

发明申请
SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
Title translation: 半导体封装结构及其制造方法

公开(公告)号：US20160300782A1

公开(公告)日：2016-10-13

申请号：US14685529

申请日：2015-04-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan CHEN , Chin-Li KAO , Kuo-Hua CHEN , Ming-Hung CHEN , Dao-Long CHEN

IPC: H01L23/495 , H01L21/56 , H01L21/48 , H01L23/00 , H01L23/31

CPC classification number: H01L23/49548 , H01L21/4825 , H01L21/565 , H01L23/3114 , H01L23/3121 , H01L23/49503 , H01L23/4952 , H01L23/49541 , H01L23/49568 , H01L23/49582 , H01L23/49816 , H01L23/5389 , H01L23/562 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/83 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/20 , H01L2224/29111 , H01L2224/29144 , H01L2224/32245 , H01L2224/32502 , H01L2224/73267 , H01L2224/8203 , H01L2224/83801 , H01L2224/83805 , H01L2224/92244 , H01L2924/15153 , H01L2924/3511 , H01L2924/3512 , H01L2924/00014

Abstract: The present disclosure relates to a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a leadframe and a semiconductor die. The leadframe includes a main portion and a protrusion portion. The semiconductor die is bonded to a first surface of the main portion. The protrusion portion protrudes from a second surface of the main portion. The position of the protrusion portion corresponds to the position of the semiconductor die.

Abstract translation: 本公开涉及一种半导体封装结构及其制造方法。半导体封装结构包括引线框和半导体管芯。引线框架包括主体部分和突出部分。半导体管芯结合到主要部分的第一表面。突出部分从主体部分的第二表面突出。突起部分的位置对应于半导体管芯的位置。

5.

发明申请
SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME 审中-公开

公开(公告)号：US20170263589A1

公开(公告)日：2017-09-14

申请号：US15416907

申请日：2017-01-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin CHANG CHIEN , Chang Chi LEE , Chin-Li KAO , Dao-Long CHEN , Ta-Chien CHENG

IPC: H01L25/065 , H01L23/00 , H01L21/56 , H01L25/00 , H01L21/78 , H01L23/31 , H01L23/367

CPC classification number: H01L25/0657 , H01L21/565 , H01L21/78 , H01L23/3121 , H01L23/3135 , H01L23/3672 , H01L24/33 , H01L25/50 , H01L2225/06541 , H01L2225/06589

Abstract: A semiconductor device package includes a package substrate, a first electronic device, a second electronic device and a first molding layer. The package substrate includes a first surface, a second surface opposite to the first surface, and an edge. The first electronic device is positioned over and electrically connected to the package substrate through the first surface. The second electronic device is positioned over and electrically connected to the first electronic device. The first molding layer is positioned over the package substrate, and the first molding layer encapsulates a portion of the first surface and the edge of the package substrate.

6.

发明申请
BUMP STRUCTURES, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PACKAGE HAVING THE SAME 有权
Title translation: BUMP结构，半导体器件和具有它们的半导体器件封装

公开(公告)号：US20160211235A1

公开(公告)日：2016-07-21

申请号：US14599366

申请日：2015-01-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Dao-Long CHEN , Ping-Feng YANG , Chang-Chi LEE , Chien-Fan CHEN

IPC: H01L23/00

CPC classification number: H01L24/13 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/14 , H01L24/16 , H01L2224/0345 , H01L2224/0346 , H01L2224/03912 , H01L2224/0401 , H01L2224/05552 , H01L2224/05647 , H01L2224/05666 , H01L2224/0614 , H01L2224/1146 , H01L2224/1147 , H01L2224/1161 , H01L2224/11849 , H01L2224/119 , H01L2224/13007 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13015 , H01L2224/1308 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/1414 , H01L2224/16055 , H01L2224/16056 , H01L2224/81191 , H01L2924/351 , H01L2924/3511 , H01L2924/3512 , H01L2924/35121 , H01L2924/00012 , H01L2924/014 , H01L2924/00014

Abstract: The present disclosure relates to bump structures and a semiconductor device and semiconductor device package having the same. The semiconductor device includes a body, at least one conductive metal pad and at least one metal pillar. The body includes a first surface. The at least one conductive metal pad is disposed on the first surface. Each metal pillar is formed on a corresponding conductive metal pad. Each metal pillar has a concave side wall and a convex side wall opposite the first concave side wall, and the concave side wall and the convex side wall are orthogonal to the corresponding conductive metal pad.

Abstract translation: 本公开涉及凸块结构以及具有该凸块结构的半导体器件和半导体器件封装。半导体器件包括主体，至少一个导电金属焊盘和至少一个金属支柱。身体包括第一表面。至少一个导电金属垫设置在第一表面上。每个金属柱形成在相应的导电金属垫上。每个金属柱具有与第一凹入侧壁相对的凹侧壁和凸侧壁，并且凹侧壁和凸侧壁与相应的导电金属垫正交。

7.

发明申请
FILLER COMPOSITIONS AND UNDERFILL COMPOSITIONS AND MOLDING COMPOUNDS INCLUDING THE SAME FOR PREPARING SEMICONDUCTOR PACKAGES 审中-公开

公开(公告)号：US20190214323A1

公开(公告)日：2019-07-11

申请号：US16354049

申请日：2019-03-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ya-Yu HSIEH , Hong-Ping LIN , Dao-Long CHEN , Ping-Feng YANG , Meng-Kai SHIH

IPC: H01L23/29 , C08G59/42 , C08K5/5435 , C08K5/544 , C08K3/04 , C08K3/36 , H01L23/00 , C09D163/00

CPC classification number: H01L23/295 , C08G59/42 , C08K3/04 , C08K3/36 , C08K5/5435 , C08K5/544 , C09D163/00 , H01L21/563 , H01L23/296 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L2224/16227 , H01L2224/2929 , H01L2224/29387 , H01L2224/29393 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73204 , H01L2224/73265 , H01L2924/01006 , H01L2924/05442 , H01L2924/0665 , H01L2924/15311 , H01L2924/3511 , H01L2924/3512 , H01L2924/00014 , H01L2924/00012

Abstract: A semiconductor package includes a filler composition, wherein the filler composition includes particles each including both carbon and silica, wherein the filler composition is substantially devoid of alumina or silicon carbide, and the filler composition has a weight ratio of carbon to silica of at least greater than 1.0.

8.

发明申请
SEMICONDUCTOR DEVICES AND SEMICONDUCTOR PACKAGES 审中-公开

公开(公告)号：US20190148326A1

公开(公告)日：2019-05-16

申请号：US16247437

申请日：2019-01-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin HUNG , Dao-Long CHEN , Ying-Ta CHIU , Ping-Feng YANG

IPC: H01L23/00

Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.

9.

发明申请
SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权

公开(公告)号：US20180114762A1

公开(公告)日：2018-04-26

申请号：US15299236

申请日：2016-10-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Ta CHIU , Chiu-Wen LEE , Dao-Long CHEN , Po-Hsien SUNG , Ping-Feng YANG , Kwang-Lung LIN

IPC: H01L23/60 , H01L23/31 , H01L23/06 , H01L23/00 , H01L21/56

CPC classification number: H01L23/60 , H01L21/56 , H01L21/565 , H01L23/06 , H01L23/10 , H01L23/3128 , H01L23/3135 , H01L23/49811 , H01L23/49827 , H01L23/552 , H01L24/49 , H01L2224/48091

Abstract: A semiconductor package structure includes a substrate, a semiconductor element, an encapsulant, an adhesion layer and a metal cap. The semiconductor element is disposed on the substrate. The encapsulant covers the semiconductor element. The adhesion layer is disposed on the encapsulant. The metal cap is attached to the encapsulant by the adhesion layer, and the metal cap is conformal with the encapsulant.