公开(公告)号：US20210327796A1

公开(公告)日：2021-10-21

申请号：US16853396

申请日：2020-04-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan CHEN ,  Chih-Pin HUNG

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00

Abstract: A wiring structure is provided. The wiring structure includes an upper redistribution structure, a lower redistribution structure, a conductive structure, an upper bonding layer and a lower bonding layer. The conductive structure is disposed between and electrically connected to the upper redistribution structure and the lower redistribution structure. The upper bonding layer is disposed between the upper redistribution structure and the conductive structure to bond the upper redistribution structure and the conductive structure together. The lower bonding layer is disposed between the lower redistribution structure and the conductive structure to bond the lower redistribution structure and the conductive structure together.

公开(公告)号：US20190127573A1

公开(公告)日：2019-05-02

申请号：US15801116

申请日：2017-11-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chean-Cheng SU ,  Chih-Pin HUNG ,  Shin-Luh TARNG ,  Chaung Chi WANG ,  Chao Ming TSENG ,  Shiu-Chih WANG

IPC: C08L67/04 ,  H01L21/673 ,  C08K5/00 ,  C08K5/09 ,  C08K3/36 ,  C08K3/04 ,  C08K5/5419

Abstract: A polylactic acid resin composition includes about 100 parts by weight of a polylactic acid resin, about 0.001 to about 3 parts by weight of a nucleating agent and about 3 to about 70 parts by weight of a filler. The polylactic acid resin composition can be processed into a biodegradable molded article or other product having a high impact strength and a high heat deflection temperature.

公开(公告)号：US20180047571A1

公开(公告)日：2018-02-15

申请号：US15615665

申请日：2017-06-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： John Richard HUNT ,  William T. Chen ,  Chih-Pin HUNG ,  Chen-Chao WANG

IPC: H01L21/108 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/528 ,  H01L23/485 ,  H01L23/04 ,  H01L23/48 ,  H01L21/768 ,  H01L27/108

CPC classification number: H01L21/108 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76801 ,  H01L23/04 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L27/10829 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81

Abstract: A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.

公开(公告)号：US20170365515A1

公开(公告)日：2017-12-21

申请号：US15184828

申请日：2016-06-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chin-Cheng KUO ,  Pao-Nan LEE ,  Chih-Pin HUNG ,  Ying-Te OU

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5286 ,  H01L24/02 ,  H01L24/05 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05562

Abstract: The present disclosure relates to a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface. The semiconductor substrate has a space extending from the second surface to the first surface and an insulation body is disposed in the space. The semiconductor package structure includes conductive posts in the insulation body.

公开(公告)号：US20230411349A1

公开(公告)日：2023-12-21

申请号：US18239722

申请日：2023-08-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan CHEN ,  Meng-Kai SHIH ,  Teck-Chong LEE ,  Shin-Luh TARNG ,  Chih-Pin HUNG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L24/33 ,  H01L24/17 ,  H01L24/73 ,  H01L23/5283 ,  H01L21/566 ,  H01L2224/02373 ,  H01L2224/73253 ,  H01L2924/3511 ,  H01L2924/381 ,  H01L2224/0231 ,  H01L2224/02381

Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.

公开(公告)号：US20200083143A1

公开(公告)日：2020-03-12

申请号：US16566502

申请日：2019-09-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Jung-Che TSAI ,  Ian HU ,  Chih-Pin HUNG

IPC: H01L23/427 ,  H01L23/36 ,  H01L23/00

Abstract: An electronic device includes a main substrate, a semiconductor package structure and at least one heat pipe. The semiconductor package structure is electrically connected to the main substrate, and includes a die mounting portion, a semiconductor die and a cover structure. The semiconductor die is disposed on the die mounting portion. The cover structure covers the semiconductor die. The heat pipe contacts the cover structure for dissipating a heat generated by the semiconductor die.

公开(公告)号：US20190103386A1

公开(公告)日：2019-04-04

申请号：US15721257

申请日：2017-09-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： William T. CHEN ,  John Richard HUNT ,  Chih-Pin HUNG ,  Chen-Chao WANG ,  Chih-Yi HUANG

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.

公开(公告)号：US20190080993A1

公开(公告)日：2019-03-14

申请号：US15702700

申请日：2017-09-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Dao-Long CHEN ,  Chih-Pin HUNG

IPC: H01L23/498 ,  H01L23/29

Abstract: A substrate including a dielectric layer and a patterned conductive layer adjacent to the dielectric layer is provided. The patterned conductive layer comprises a first conductive pad, the first conductive pad comprises a first portion having a first concave sidewall. The substrate further includes a protection layer disposed on the patterned conductive layer, and the protection layer covers the first portion of the first conductive pad.

公开(公告)号：US20170200702A1

公开(公告)日：2017-07-13

申请号：US15404093

申请日：2017-01-11

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin HUNG ,  Ying-Te OU ,  Pao-Nan LEE

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L23/5226 ,  H01L23/528 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2924/10253 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: In one or more embodiments, a semiconductor device includes a substrate, a first dielectric layer and a first conductive layer. The substrate includes a first surface and a second surface opposite the first surface. The first dielectric layer is on the first surface of the substrate. The first conductive layer is on the first surface of the substrate and includes a first portion on the first dielectric layer and a second portion surrounded by the first dielectric layer. The second portion of the first conductive layer extends from the first portion of the first conductive layer through the first dielectric layer to contact the first surface of the substrate.

公开(公告)号：US20220084972A1

公开(公告)日：2022-03-17

申请号：US17534358

申请日：2021-11-23

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Mei-Ju LU ,  Chi-Han CHEN ,  Chang-Yu LIN ,  Jr-Wei LIN ,  Chih-Pin HUNG

IPC: H01L23/00

Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.