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    PACKAGE STRUCTURE AND TESTING METHOD
    1.
    发明申请
    PACKAGE STRUCTURE AND TESTING METHOD 有权

    公开(公告)号：US20210278457A1

    公开(公告)日：2021-09-09

    申请号：US16812232

    申请日：2020-03-06

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Chen-Chao WANG ,  Tsung-Tang TSAI ,  Chih-Yi HUANG

    IPC: G01R31/28 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/18

    Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.

    SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    2.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权

    公开(公告)号：US20220399240A1

    公开(公告)日：2022-12-15

    申请号：US17893033

    申请日：2022-08-22

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Chen-Chao WANG ,  Chih-Yi HUANG ,  Keng-Tuan CHANG

    IPC: H01L21/66 ,  H01L25/00 ,  H01L23/485 ,  H01L23/498 ,  H01L25/065

    Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.

    SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    3.
    发明公开
    SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240186193A1

    公开(公告)日：2024-06-06

    申请号：US18439743

    申请日：2024-02-12

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Chen-Chao WANG ,  Chih-Yi HUANG ,  Keng-Tuan CHANG

    IPC: H01L21/66 ,  H01L23/485 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

    CPC classification number: H01L22/22 ,  H01L23/485 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/50

    Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.

    ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    4.
    发明申请
    ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220384381A1

    公开(公告)日：2022-12-01

    申请号：US17334622

    申请日：2021-05-28

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Chung-Hung LAI ,  Chin-Li KAO ,  Chih-Yi HUANG ,  Teck-Chong LEE

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/14 ,  H01L25/065

    Abstract: An electronic device package is provided. The electronic device package includes a redistribution layer (RDL), a first electronic component and an interconnector. The RDL includes a topmost circuit layer, and the topmost circuit layer includes a conductive trace. The first electronic component is disposed over the RDL. The interconnector is disposed between the RDL and the first electronic component. A direction is defined by extending from a center of the first electronic component toward an edge of the first electronic component, and the direction penetrates a first sidewall and a second sidewall of the interconnector, the second sidewall is farther from the center of the first electronic component than the first sidewall is, and the conductive trace is outside a projection region of the second sidewall.

    ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220352066A1

    公开(公告)日：2022-11-03

    申请号：US17243456

    申请日：2021-04-28

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Shao-An CHEN ,  Chih-Yi HUANG ,  Ping Cing SHEN

    IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L21/66 ,  H01L21/48

    Abstract: An electronic device package includes an encapsulated electronic component, a redistribution layer (RDL) and a conductive via. The RDL is disposed above the encapsulated electronic component. The RDL includes a circuit layer comprising a conductive pad including a pad portion having a curved edge and a center of curvature, and an extension portion protruding from the pad portion and having a curved edge and a center of curvature. The circuit layer further includes a dielectric layer above the RDL. The conductive via is disposed in the dielectric layer and connected to the conductive pad of the RDL. A center of the conductive via is closer to the center of curvature of the edge of the extension portion than to the center of curvature of the edge of the pad portion.

    SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权

    公开(公告)号：US20220115276A1

    公开(公告)日：2022-04-14

    申请号：US17067565

    申请日：2020-10-09

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Chen-Chao WANG ,  Chih-Yi HUANG ,  Keng-Tuan CHANG

    IPC: H01L21/66 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/485

    Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.

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