Invention Publication
- Patent Title: PACKAGE STRUCTURE AND TESTING METHOD
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Application No.: US18236930Application Date: 2023-08-22
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Publication No.: US20230393194A1Publication Date: 2023-12-07
- Inventor: Chen-Chao WANG , Tsung-Tang TSAI , Chih-Yi HUANG
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaohsiung
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW Kaohsiung
- Main IPC: G01R31/28
- IPC: G01R31/28 ; H01L23/498 ; H01L23/538 ; H01L23/552 ; H01L25/18 ; H01L23/00

Abstract:
A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.
Public/Granted literature
- US12216157B2 Package structure and testing method Public/Granted day:2025-02-04
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