公开(公告)号：US12131997B2

公开(公告)日：2024-10-29

申请号：US17844337

申请日：2022-06-20

Applicant: SK hynix Inc.

Inventor： Won Duck Jung

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/552 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/5286 ,  H01L23/528 ,  H01L23/552 ,  H01L24/05 ,  H01L24/46 ,  H01L25/0657 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48228 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A semiconductor package is configured to include a package substrate, a semiconductor chip disposed on the package substrate, and bonding wires. The package substrate includes a first column of bond fingers disposed in a first layer and a second column of bond fingers disposed in a second layer. The semiconductor chip includes a first column of chip pads arrayed in a first column and a second column of chip pads arrayed in a second column adjacent to the first column. The first column of chip pads are connected to the first column of bond fingers, respectively, through first bonding wires, and the second column of chip pads are connected to the second column of bond fingers, respectively, through second bonding wires.

公开(公告)号：US12033946B2

公开(公告)日：2024-07-09

申请号：US17752293

申请日：2022-05-24

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Ji Young Chung ,  Seung Chul Jang ,  Ron Huemoeller

IPC: H01L23/538 ,  H01L23/552 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L23/552 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: In one example, an electronic assembly comprises a first semiconductor device and a second semiconductor device. Each of the first semiconductor device and the second semiconductor devices comprises a substrate comprising a top surface and a conductive structure, an electronic component over the top surface of the substrate, a dielectric material over the top surface of the substrate and contacting a side of the electronic component, a substrate tab at an end of substrate and not covered by the dielectric material, wherein the conductive structure of the substrate is exposed at the substrate tab, and an interconnect electrically coupled to the conductive structure at the substrate tab of the first semiconductor device and the conductive structure at the substrate tab of the second semiconductor device. Other examples and related methods are also disclosed herein.

公开(公告)号：US11923319B2

公开(公告)日：2024-03-05

申请号：US17117547

申请日：2020-12-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Woo Park

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/053 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/552 ,  H01L21/4817 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/053 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/48157 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/3025

Abstract: A method of fabricating a semiconductor package includes mounting at least one semiconductor chip to a package substrate, forming a shielding wall around the at least one semiconductor chip, forming a molded body on the package substrate in a space surrounded by the shielding wall, and forming a shielding cover covering the molding unit and in contact with the shielding wall.

公开(公告)号：US11670618B2

公开(公告)日：2023-06-06

申请号：US17008918

申请日：2020-09-01

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  YongMin Kim ,  JaeHyuk Choi ,  YeoChan Ko ,  HeeSoo Lee

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/552 ,  H01L21/683 ,  H01L23/31 ,  H01L25/16 ,  H01L23/00 ,  H01L21/66 ,  H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/50

CPC classification number: H01L25/0655 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/566 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/552 ,  H01L25/0652 ,  H01L25/16 ,  H01L25/50 ,  H01L21/486 ,  H01L22/14 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06572 ,  H01L2924/0105 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/11901 ,  H01L2224/11849 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/05111 ,  H01L2924/00014 ,  H01L2224/05155 ,  H01L2924/00014 ,  H01L2224/05144 ,  H01L2924/00014 ,  H01L2224/05139 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05611 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2924/00014 ,  H01L2224/13124 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13155 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13116 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13113 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/013 ,  H01L2924/01082 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/013 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2224/13116 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81424 ,  H01L2924/00014 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2224/81411 ,  H01L2924/00014 ,  H01L2224/81455 ,  H01L2924/00014 ,  H01L2224/81444 ,  H01L2924/00014 ,  H01L2224/81439 ,  H01L2924/00014 ,  H01L2224/81466 ,  H01L2924/00014 ,  H01L2224/81484 ,  H01L2924/00014

Abstract: A semiconductor device includes a substrate with an opening formed through the substrate. A first electronic component is disposed over the substrate outside a footprint of the first opening. A second electronic component is disposed over the substrate opposite the first electrical component. A third electronic component is disposed over the substrate adjacent to the first electronic component. The substrate is disposed in a mold including a second opening of the mold over a first side of the substrate. The mold contacts the substrate between the first electronic component and the third electronic component. An encapsulant is deposited into the second opening. The encapsulant flows through the first opening to cover a second side of the substrate. In some embodiments, a mold film is disposed in the mold, and an interconnect structure on the substrate is embedded in the mold film.

公开(公告)号：US09997466B2

公开(公告)日：2018-06-12

申请号：US15352405

申请日：2016-11-15

Applicant: Honeywell International Inc.

Inventor： Eric E. Vogt ,  Gregor D. Dougal ,  James L. Tucker

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L23/13 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L23/57 ,  H01L23/573 ,  H01L24/05 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2224/81896 ,  H01L2224/83805 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer layer. The interposer layer may include at least one integrated circuit die and an interposer portion that includes a plurality of electrically conductive pillars arranged in a laterally patterned array within the interposer layer.

公开(公告)号：US09980385B2

公开(公告)日：2018-05-22

申请号：US15494672

申请日：2017-04-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andreas Huber ,  Harald Huels ,  Stefano S. Oggioni ,  Thomas Strach ,  Thomas-Michael Winkel

IPC: H05K1/18 ,  H05K1/14 ,  H05K3/46 ,  H05K3/18 ,  H05K3/00 ,  H05K1/11 ,  H05K3/34 ,  H05K1/02

CPC classification number: H05K1/183 ,  H01L23/49838 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06537 ,  H01L2225/06548 ,  H05K1/0219 ,  H05K1/115 ,  H05K1/144 ,  H05K1/181 ,  H05K3/0097 ,  H05K3/18 ,  H05K3/34 ,  H05K3/4697 ,  H05K2201/049 ,  H05K2201/10015 ,  H05K2201/10106

Abstract: The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.

公开(公告)号：US20180130756A1

公开(公告)日：2018-05-10

申请号：US15867080

申请日：2018-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shou-Zen CHANG ,  Chi-Ming HUANG ,  Kai-Chiang WU ,  Sen-Kuei HSU ,  Hsin-Yu PAN ,  Han-Ping PU ,  Albert WAN

IPC: H01L23/552 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/5382 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06537 ,  H01L2225/06555

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device. The semiconductor device structure includes a conductive element over the first device. The semiconductor device structure includes a first conductive shielding layer between the first device and the conductive element. The first conductive shielding layer has openings, and a maximum width of the opening is less than a wavelength of an energy generated by the first device. The semiconductor device structure includes a second conductive shielding layer under the first device. The first device is between the first conductive shielding layer and the second conductive shielding layer, and the second conductive shielding layer has a plurality of second openings.

公开(公告)号：US09935058B2

公开(公告)日：2018-04-03

申请号：US15357578

申请日：2016-11-21

Applicant: International Business Machines Corporation

Inventor： Mark C. Lamorey ,  Janak G. Patel ,  Peter Slota, Jr. ,  David B. Stone

IPC: H01L21/00 ,  H01L23/552 ,  H01L23/367 ,  H01L23/498 ,  H01L23/50 ,  H01L23/64 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H05K1/02 ,  H05K1/14 ,  H01L25/16 ,  H05K1/16

CPC classification number: H01L23/552 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/642 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1624 ,  H01L2224/17181 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1659 ,  H01L2924/16747 ,  H02J7/0042 ,  H02J7/0052 ,  H02J7/345 ,  H05K1/0204 ,  H05K1/021 ,  H05K1/0215 ,  H05K1/0216 ,  H05K1/144 ,  H05K1/162 ,  H05K2201/0116 ,  H05K2201/0187 ,  H05K2201/041 ,  H05K2201/0999 ,  H05K2201/10515 ,  H05K2201/1056 ,  H01L2924/014 ,  H01L2924/00

Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

公开(公告)号：US09887163B2

公开(公告)日：2018-02-06

申请号：US15088206

申请日：2016-04-01

Applicant: Hana Micron Inc.

Inventor： Hyun Joo Kim ,  Seung Hwan Lee

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L21/60

CPC classification number: H01L23/552 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/97 ,  H01L2021/60022 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06558 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00

Abstract: The present invention relates to a semiconductor package and a method of manufacturing the same. Specifically, the present invention relates to a semiconductor package including a substrate; a semiconductor chip mounted on the substrate; a connection element including an insulator mounted on the substrate and a first connection part of a conductive material formed at an end of the insulator; a molding part surrounding the semiconductor chip, and sealing the connection element for an upper surface of the first connection part to be exposed; and a shield layer surrounding the molding part, and forming an opening part on a part corresponding to the first connection part.

公开(公告)号：US09853016B2

公开(公告)日：2017-12-26

申请号：US15435719

申请日：2017-02-17

Applicant: Apple Inc.

Inventor： Anthony Fai ,  Evan R. Boyle ,  Zhiping Yang ,  Zhonghua Wu

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5384 ,  H01L23/552 ,  H01L23/60 ,  H01L24/06 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/065 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/06151 ,  H01L2224/06177 ,  H01L2224/1405 ,  H01L2224/1414 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.