Patent search ap:("Apple Inc.") AND inv:"Zhiping Yang" Page 1

1.

发明申请
SYSTEMS AND METHODS FOR HIGH-SPEED, LOW-PROFILE MEMORY PACKAGES AND PINOUT DESIGNS 审中-公开
Title translation: 用于高速，低配置的存储器封装和引脚排列设计的系统和方法

公开(公告)号：US20170005056A1

公开(公告)日：2017-01-05

申请号：US15266752

申请日：2016-09-15

Applicant: Apple Inc.

Inventor： Anthony Fai , Evan R. Boyle , Zhiping Yang , Zhonghua Wu

IPC: H01L23/00 , H01L25/065

CPC classification number: H01L25/0657 , H01L21/4853 , H01L21/486 , H01L21/56 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5283 , H01L23/5286 , H01L23/5384 , H01L23/552 , H01L23/60 , H01L24/06 , H01L24/14 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/85 , H01L25/065 , H01L25/18 , H01L25/50 , H01L2224/04042 , H01L2224/05599 , H01L2224/06151 , H01L2224/06177 , H01L2224/1405 , H01L2224/1414 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2224/85399 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06537 , H01L2225/06548 , H01L2225/06555 , H01L2225/06562 , H01L2924/00014 , H01L2924/1443 , H01L2924/15311 , H01L2924/15312 , H01L2924/15313 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

Abstract translation: 为层叠半导体存储器封装提供了系统和方法。每个封装可以包括集成电路（“IC”）封装基板，能够通过两个通道将数据传输到堆叠在封装内的存储器管芯。每个通道可以位于IC封装衬底的一侧，并且来自每个通道的信号可以从它们各自的侧面被引导到存储器管芯。

2.

发明授权
Methods and apparatus for equalization of a high speed serial bus 有权

公开(公告)号：US10002101B2

公开(公告)日：2018-06-19

申请号：US14641170

申请日：2015-03-06

Applicant: Apple Inc.

Inventor： Songping Wu , Zhiping Yang , Kirill Kalinichev , Greg Nayman , Georgi Beloev

IPC: G06F13/00 , G06F13/42 , G06F13/40 , G06F1/32

CPC classification number: G06F13/4282 , G06F1/3287 , G06F13/4022

Abstract: Methods and apparatus for equalization of a high speed serial bus. A well-tuned passive equalization circuit for use with high frequency differential signals suffer from e.g., impedance mismatches, impedance discontinuities (e.g., connectors, etc.). In one embodiment, a shunting circuit is inserted between the differential terminals of a Universal Serial Bus (USB) cable, connector, etc. The shunting circuit is configured to “open” at low frequencies to enable Full Speed (FS) enumeration, while also providing sufficiently high impedance at high frequencies to enable High Speed (HS) operation. In one such implementation, the shunting circuit includes a tuned resistor, capacitor, inductor, and switch element arranged in series.

3.

发明授权
Systems and methods for high-speed, low-profile memory packages and pinout designs 有权

公开(公告)号：US09853016B2

公开(公告)日：2017-12-26

申请号：US15435719

申请日：2017-02-17

Applicant: Apple Inc.

Inventor： Anthony Fai , Evan R. Boyle , Zhiping Yang , Zhonghua Wu

IPC: H01L25/065 , H01L25/00 , H01L23/498

CPC classification number: H01L25/0657 , H01L21/4853 , H01L21/486 , H01L21/56 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5283 , H01L23/5286 , H01L23/5384 , H01L23/552 , H01L23/60 , H01L24/06 , H01L24/14 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/85 , H01L25/065 , H01L25/18 , H01L25/50 , H01L2224/04042 , H01L2224/05599 , H01L2224/06151 , H01L2224/06177 , H01L2224/1405 , H01L2224/1414 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2224/85399 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06537 , H01L2225/06548 , H01L2225/06555 , H01L2225/06562 , H01L2924/00014 , H01L2924/1443 , H01L2924/15311 , H01L2924/15312 , H01L2924/15313 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

4.

发明授权
Systems and methods for high-speed, low-profile memory packages and pinout designs 有权

公开(公告)号：US09466571B2

公开(公告)日：2016-10-11

申请号：US14802750

申请日：2015-07-17

Applicant: Apple Inc.

Inventor： Anthony Fai , Evan R. Boyle , Zhiping Yang , Zhonghua Wu

IPC: H01L23/48 , H01L23/52 , H01L29/40 , H01L23/538 , H01L23/498 , H01L23/00 , H01L23/60 , H01L23/528 , H01L21/48 , H01L25/00 , H01L21/56 , H01L25/065 , H01L25/18 , H01L23/552

CPC classification number: H01L25/0657 , H01L21/4853 , H01L21/486 , H01L21/56 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5283 , H01L23/5286 , H01L23/5384 , H01L23/552 , H01L23/60 , H01L24/06 , H01L24/14 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/85 , H01L25/065 , H01L25/18 , H01L25/50 , H01L2224/04042 , H01L2224/05599 , H01L2224/06151 , H01L2224/06177 , H01L2224/1405 , H01L2224/1414 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2224/85399 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06537 , H01L2225/06548 , H01L2225/06555 , H01L2225/06562 , H01L2924/00014 , H01L2924/1443 , H01L2924/15311 , H01L2924/15312 , H01L2924/15313 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

5.

发明申请
SYSTEMS AND METHODS FOR HIGH-SPEED, LOW-PROFILE MEMORY PACKAGES AND PINOUT DESIGNS 审中-公开
Title translation: 用于高速，低配置的存储器封装和引脚排列设计的系统和方法

公开(公告)号：US20150325560A1

公开(公告)日：2015-11-12

申请号：US14802750

申请日：2015-07-17

Applicant: Apple Inc.

Inventor： Anthony Fai , Evan R. Boyle , Zhiping Yang , Zhonghua Wu

IPC: H01L25/18 , H01L23/00 , H01L23/60 , H01L21/56 , H01L21/48 , H01L25/065 , H01L25/00 , H01L23/498 , H01L23/528

CPC classification number: H01L25/0657 , H01L21/4853 , H01L21/486 , H01L21/56 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5283 , H01L23/5286 , H01L23/5384 , H01L23/552 , H01L23/60 , H01L24/06 , H01L24/14 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/85 , H01L25/065 , H01L25/18 , H01L25/50 , H01L2224/04042 , H01L2224/05599 , H01L2224/06151 , H01L2224/06177 , H01L2224/1405 , H01L2224/1414 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2224/85399 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06537 , H01L2225/06548 , H01L2225/06555 , H01L2225/06562 , H01L2924/00014 , H01L2924/1443 , H01L2924/15311 , H01L2924/15312 , H01L2924/15313 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

Abstract translation: 为层叠半导体存储器封装提供了系统和方法。每个封装可以包括集成电路（“IC”）封装基板，能够通过两个通道将数据传输到堆叠在封装内的存储器管芯。每个通道可以位于IC封装衬底的一侧，并且来自每个通道的信号可以从它们各自的侧面被引导到存储器管芯。

6.

发明申请
Capacitive Sensing Array Having Electrical Isolation 审中-公开

公开(公告)号：US20190266375A1

公开(公告)日：2019-08-29

申请号：US16412234

申请日：2019-05-14

Applicant: Apple Inc.

Inventor： Zhiping Yang , Hanfeng Wang

IPC: G06K9/00

Abstract: A capacitive fingerprint sensor that may be formed of an array of sensing elements. Each capacitive sensing element of the array may register a voltage that varies with the capacitance of a capacitive coupling. A finger may capacitively couple to the individual capacitive sensing elements of the sensor, such that the sensor may sense a capacitance between each capacitive sensing element and the flesh of the fingerprint. The capacitance signal may be detected by sensing the change in voltage on the capacitive sensing element as the relative voltage between the finger and the sensing chip is changed. Alternately, the capacitance signal may be detected by sensing the change in charge received by the capacitive sensing elements as the relative voltage between the finger and the sensing chip is changed.

7.

发明申请
Capacitive Sensing Array Having Electrical Isolation 审中-公开
Title translation: 具有电气隔离的电容式感应阵列

公开(公告)号：US20150070079A1

公开(公告)日：2015-03-12

申请号：US14022058

申请日：2013-09-09

Applicant: APPLE INC.

Inventor： Zhiping Yang , Hanfeng Wang

IPC: H03K17/96

CPC classification number: G06K9/0002

Abstract: A capacitive fingerprint sensor that may be formed of an array of sensing elements. Each capacitive sensing element of the array may register a voltage that varies with the capacitance of a capacitive coupling. A finger may capacitively couple to the individual capacitive sensing elements of the sensor, such that the sensor may sense a capacitance between each capacitive sensing element and the flesh of the fingerprint. The capacitance signal may be detected by sensing the change in voltage on the capacitive sensing element as the relative voltage between the finger and the sensing chip is changed. Alternately, the capacitance signal may be detected by sensing the change in charge received by the capacitive sensing elements as the relative voltage between the finger and the sensing chip is changed.

Abstract translation: 可以由感测元件阵列形成的电容式指纹传感器。阵列的每个电容感测元件可以记录随电容耦合的电容而变化的电压。手指可以电容地耦合到传感器的各个电容感测元件，使得传感器可感测每个电容感测元件与指纹的肉体之间的电容。可以通过感测手指和感测芯片之间的相对电压改变来检测电容感测元件上的电压变化来检测电容信号。或者，可以通过感测由手指和感测芯片之间的相对电压改变而由电容式感测元件接收的电荷的变化来检测电容信号。

8.

发明授权
Capacitive sensing array having electrical isolation 有权

公开(公告)号：US10296773B2

公开(公告)日：2019-05-21

申请号：US14022058

申请日：2013-09-09

Applicant: Apple Inc.

Inventor： Zhiping Yang , Hanfeng Wang

IPC: H03K17/96 , G06K9/00

Abstract: A capacitive fingerprint sensor that may be formed of an array of sensing elements. Each capacitive sensing element of the array may register a voltage that varies with the capacitance of a capacitive coupling. A finger may capacitively couple to the individual capacitive sensing elements of the sensor, such that the sensor may sense a capacitance between each capacitive sensing element and the flesh of the fingerprint. The capacitance signal may be detected by sensing the change in voltage on the capacitive sensing element as the relative voltage between the finger and the sensing chip is changed. Alternately, the capacitance signal may be detected by sensing the change in charge received by the capacitive sensing elements as the relative voltage between the finger and the sensing chip is changed.