公开(公告)号：US20240363604A1

公开(公告)日：2024-10-31

申请号：US18432387

申请日：2024-02-05

Applicant: pSemi Corporation

Inventor： David GIULIANO

IPC: H01L25/16 ,  H01L23/48 ,  H01L23/522 ,  H01L23/64 ,  H01L27/01 ,  H01L27/06 ,  H02M3/07 ,  H05K1/02 ,  H05K1/11 ,  H10N19/00

CPC classification number: H01L25/16 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/64 ,  H01L23/642 ,  H01L27/016 ,  H01L27/0688 ,  H01L28/40 ,  H01L28/90 ,  H02M3/07 ,  H05K1/0298 ,  H05K1/115 ,  H10N19/00 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H02M3/077

Abstract: This disclosure relates to embodiments that include an apparatus that may comprise a first layer including a first plurality of active devices, a second layer including a second plurality of active devices, and/or a third layer including a plurality of passive devices and disposed between the first and the second layers. An active device of the first plurality of active devices and an active device of the second plurality of active devices may influence a state of charge of a passive device of the plurality of passive devices.

公开(公告)号：US20240258288A1

公开(公告)日：2024-08-01

申请号：US18160818

申请日：2023-01-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Shibuya ,  Kwang-Soo Kim

IPC: H01L25/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L25/165 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49555 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45541 ,  H01L2224/45624 ,  H01L2224/45647 ,  H01L2224/48245 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104

Abstract: In a described example, an apparatus includes: a package substrate with conductive leads; a semiconductor die mounted to the package substrate, the semiconductor die having a first thickness; electrical connections coupling bond pads on the semiconductor die to conductive leads on the package substrate; brackets attached to the package substrate spaced from the semiconductor die and extending away from the package substrate to a distance from the package substrate that is greater than the first thickness of the semiconductor die; and mold compound covering the package substrate, the semiconductor die, the brackets, and the semiconductor die to form a semiconductor device package having a board side surface and a top surface opposite the board side surface, and having portions of the brackets exposed from the mold compound on the top surface of the semiconductor device package to form mounts for a passive component.

公开(公告)号：US20240243012A1

公开(公告)日：2024-07-18

申请号：US18622588

申请日：2024-03-29

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L21/77 ,  H01L21/66 ,  H01L23/00 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L21/77 ,  H01L22/20 ,  H01L24/32 ,  H01L24/73 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18 ,  H01L24/17 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/24195 ,  H01L2924/12 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Systems including voltage regulator circuits are disclosed. In one embodiment, an apparatus includes a voltage regulator controller integrated circuit (IC) die including one or more portions of a voltage regulator circuit. The apparatus further includes a capacitor die, an inductor die, and an interconnect layer arranged over the voltage regulator controller IC die, the capacitor die and the inductor die. The interconnect provides electrical connections between the voltage regulator controller IC die, the capacitor die and the inductor die to form the voltage regulator circuit. In a further embodiment, the voltage regulator controller IC die, the capacitor die and the inductor die are arranged in a planar fashion within a voltage regulator module. In still another embodiment, a system IC is coupled to the voltage regulator module and includes one or more functional circuit blocks coupled to receive a regulated supply voltage generated by the voltage regulator circuit.

公开(公告)号：US12027487B2

公开(公告)日：2024-07-02

申请号：US18145310

申请日：2022-12-22

Applicant: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/80 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05684 ,  H01L2224/11009 ,  H01L2224/11464 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13084 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13655 ,  H01L2224/13684 ,  H01L2224/13686 ,  H01L2224/13805 ,  H01L2224/13809 ,  H01L2224/13811 ,  H01L2224/13844 ,  H01L2224/13847 ,  H01L2224/13855 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/16265 ,  H01L2224/16268 ,  H01L2224/16501 ,  H01L2224/2919 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81026 ,  H01L2224/81065 ,  H01L2224/81099 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/83026 ,  H01L2224/83815 ,  H01L2225/06513 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/3841

Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

公开(公告)号：US20240178172A1

公开(公告)日：2024-05-30

申请号：US18432788

申请日：2024-02-05

Applicant: SK hynix Inc.

Inventor： Chan Ho YOON

IPC: H01L23/00 ,  H01L23/522 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L23/5228 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511 ,  H01L2924/19043 ,  H01L2924/19104

Abstract: A semiconductor device includes a first pad defined on one surface of a first chip; a second pad defined on one surface of a second chip which is stacked on the first chip, and bonded to the first pad; a first resistor element defined in the first chip, and coupled to the first pad; and a second resistor element defined in the second chip, and coupled to the second pad.

公开(公告)号：US11984246B2

公开(公告)日：2024-05-14

申请号：US17566529

申请日：2021-12-30

Applicant: Intel Corporation

Inventor： Andreas Wolter ,  Thorsten Meyer ,  Gerhard Knoblinger

IPC: H01F17/00 ,  H01F41/04 ,  H01L23/00 ,  H01L23/522 ,  H01L23/64 ,  H01F27/28

CPC classification number: H01F17/0033 ,  H01F41/046 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/17 ,  H01F2017/0086 ,  H01F2027/2814 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/16265 ,  H01L2224/16267 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/03462 ,  H01L2924/00014 ,  H01L2224/03464 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/1132 ,  H01L2924/00014 ,  H01L2224/11334 ,  H01L2924/00014

Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

公开(公告)号：US20240128248A1

公开(公告)日：2024-04-18

申请号：US18365455

申请日：2023-08-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Hiroshi MIYAKI ,  Takayuki IGARASHI

IPC: H01L25/16 ,  H01F27/28 ,  H01F27/30 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01F27/2804 ,  H01F27/306 ,  H01L24/32 ,  H01F27/324 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/32265 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48265 ,  H01L2224/73265 ,  H01L2924/19042 ,  H01L2924/19104

Abstract: A semiconductor device includes an insulating substrate and an upper inductor that is formed on the insulating substrate and is a component of a transformer that performs contactless communication between different potentials. Here, the upper inductor is configured to be applied with a first potential. The upper inductor is formed so as to be magnetically coupled to a lower inductor that is configured to be applied with a second potential different from the first potential.

公开(公告)号：US11948871B2

公开(公告)日：2024-04-02

申请号：US17325197

申请日：2021-05-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Yogesh Kumar Ramadass ,  Salvatore Frank Pavone ,  Mahmud Halim Chowdhury

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49589 ,  H01L23/4951 ,  H01L23/49524 ,  H01L24/32 ,  H01L24/73 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/16245 ,  H01L2224/32265 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/9211 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Disclosed embodiments include an integrated circuit (IC) comprising a silicon wafer, first and second conductive lines on the silicon wafer. There are first, second and third insulation blocks with portions on the first and second conductive lines and the silicon wafer, a metal pillar on the surface of the first conductive line opposite the silicon wafer, and a conductive adhesive block on the surface of the second conductive line opposite the silicon wafer. The IC also has a lead frame having first and second leads, and a capacitor having first and second capacitor terminals in which the first capacitor terminal is connected to the second lead using conductive adhesive, the second capacitor terminal is connected to the second conductive line through the conductive adhesive block, and the first lead is coupled to the first conductive line.

公开(公告)号：US20240021592A1

公开(公告)日：2024-01-18

申请号：US18466207

申请日：2023-09-13

Applicant: ROHM CO., LTD.

Inventor： Isamu NISHIMURA ,  Mamoru YAMAGAMI

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L25/16 ,  H01L24/16 ,  H01L23/3121 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L28/10 ,  H01L24/13 ,  H01L2224/16227 ,  H01L2924/19104 ,  H01L2924/19042 ,  H01L2224/13083 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13144 ,  H01L2224/13111

Abstract: A semiconductor device includes a substrate having a main surface, a plurality of first wirings, each having a first embedded part embedded in the substrate and exposed from the main surface, and a mounted part which is in contact with the main surface and is connected to the first embedded part, a semiconductor element having an element rear surface and a plurality of electrodes bonded to the mounted parts, a plurality of second wirings, each having a second embedded part embedded in the substrate and exposed from the main surface and a columnar part protruding from the second embedded part in the thickness direction, and being located outward from the semiconductor element as viewed in the thickness direction; and a passive element located on the side facing the main surface in the thickness direction more than the semiconductor element, and electrically connected to the plurality of second wirings.

公开(公告)号：US11848262B2

公开(公告)日：2023-12-19

申请号：US17176678

申请日：2021-02-16

Applicant: Infineon Technologies AG

Inventor： Angela Kessler ,  Robert Carroll ,  Robert Fehler

IPC: H01L23/498 ,  H01L25/07 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49844 ,  H01L21/4853 ,  H01L24/16 ,  H01L25/072 ,  H01L2224/16227 ,  H01L2924/19104

Abstract: A semiconductor assembly includes an interposer that includes an insulating substrate, a plurality of upper contact pads on an upper surface of the substrate, and a plurality of lower contact pads on a lower surface of the substrate, a semiconductor package that includes a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body, a first passive electrical element that includes first and second terminals, a first electrical connection between the first terminal of the first passive electrical element and a first one of the lower contact pads via the interposer, a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals, and a third electrical connection between a second one of the package terminals and a second one of the lower contact pads via the interposer.