公开(公告)号：US20240365469A1

公开(公告)日：2024-10-31

申请号：US18566430

申请日：2022-04-22

申请人： FUJIKURA PRINTED CIRCUITS LTD.

发明人： Daisuke Arai ,  Toshiya Iwamura

IPC分类号： H05K1/11 ,  G03F1/50 ,  G03F7/00 ,  G03F7/20 ,  H05K1/02 ,  H05K3/00 ,  H05K3/06

CPC分类号： H05K1/118 ,  G03F1/50 ,  G03F7/2016 ,  G03F7/70475 ,  H05K1/0281 ,  H05K3/0082 ,  H05K3/064

摘要： A method for producing a flexible printed wiring board using a photoresist includes placing the photoresist, including a first region and a second region, on a substrate, placing a first photomask including a first light-transmitting portion such that the first light-transmitting portion faces the first region to expose the photoresist through the first light-transmitting portion, and placing a second photomask including a second light-transmitting portion such that the second light-transmitting portion faces the second region to expose the photoresist through the second light-transmitting portion. The first region is adjacent to the second region such that an edge portion of the first region overlaps an edge portion of the second region. The first light-transmitting portion has a linear shape including a first tip having a tapered shape.

公开(公告)号：US12131985B2

公开(公告)日：2024-10-29

申请号：US17470519

申请日：2021-09-09

申请人： CORNING INCORPORATED

发明人： Mandakini Kanungo ,  Prantik Mazumder ,  Chukwudi Azubuike Okoro ,  Ah-Young Park ,  Scott Christopher Pollard ,  Rajesh Vaddi

IPC分类号： C25D3/38 ,  C03C3/06 ,  C03C15/00 ,  C03C17/06 ,  C03C17/10 ,  C03C23/00 ,  C23C14/18 ,  C23C18/38 ,  C23C28/02 ,  H01L21/48 ,  H01L21/768 ,  H01L23/15 ,  H01L23/48 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/38 ,  C03C3/076 ,  C25D7/12 ,  H01L23/00 ,  H01L23/492 ,  H05K3/00 ,  H05K3/42

CPC分类号： H01L23/49827 ,  C03C3/06 ,  C03C15/00 ,  C03C17/06 ,  C03C17/10 ,  C03C23/0025 ,  C23C14/18 ,  C23C18/38 ,  C23C28/02 ,  H01L21/76877 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49838 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/388 ,  C03C3/076 ,  C03C2218/115 ,  C25D3/38 ,  C25D7/123 ,  H01L21/486 ,  H01L23/4924 ,  H01L23/49866 ,  H01L23/564 ,  H05K3/002 ,  H05K3/0029 ,  H05K3/0055 ,  H05K3/423 ,  H05K3/425 ,  H05K3/428 ,  H05K2201/068 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2201/0989 ,  H05K2201/10378 ,  H05K2203/1194 ,  H05K2203/1361 ,  H05K2203/143 ,  H05K2203/1438 ,  H05K2203/162 ,  Y10T428/24273 ,  Y10T428/24479 ,  Y10T428/24851 ,  Y10T428/24917 ,  Y10T428/24926

摘要： According to various embodiments described herein, an article comprises a glass or glass-ceramic substrate having a first major surface and a second major surface opposite the first major surface, and a via extending through the substrate from the first major surface to the second major surface over an axial length in an axial direction. The article further comprises a helium hermetic adhesion layer disposed on the interior surface; and a metal connector disposed within the via, wherein the metal connector is adhered to the helium hermetic adhesion layer. The metal connector coats the interior surface of the via along the axial length of the via to define a first cavity from the first major surface to a first cavity length, the metal connector comprising a coating thickness of less than 12 μm at the first major surface. Additionally, the metal connector coats the interior surface of the via along the axial length of the via to define a second cavity from the second major surface to a second cavity length, the metal connector comprising a coating thickness of less than 12 μm at the second major surface and fully fills the via between the first cavity and the second cavity.

公开(公告)号：US20240357739A1

公开(公告)日：2024-10-24

申请号：US18639407

申请日：2024-04-18

申请人： TOPPAN Holdings Inc.

发明人： Tomoyuki Ishii

IPC分类号： H05K1/03 ,  H05K3/00 ,  H05K3/46

CPC分类号： H05K1/0306 ,  H05K3/0017 ,  H05K3/4644 ,  H05K2201/0266 ,  H05K2201/0338 ,  H05K2201/09154 ,  H05K2203/0548 ,  H05K2203/1105

摘要： A wiring board includes: a substrate; a first seed layer provided on the substrate; a first conductive layer provided on the first seed layer; a first insulating layer provided on the first conductive layer; a second seed layer provided on the first insulating layer; and a second conductive layer provided on the second seed layer. An area of the first insulating layer is smaller than an area of the first conductive layer. An area of the second conductive layer is smaller than the area of the first insulating layer. A region of the first insulating layer not overlapping the second conductive layer includes a first region surrounding the second conductive layer and a second region outside the first region. A surface roughness of the second region is larger than a surface roughness of the first region.

公开(公告)号：US20240355767A1

公开(公告)日：2024-10-24

申请号：US18761675

申请日：2024-07-02

申请人： Infineon Technologies AG

发明人： Petteri Palm ,  Thorsten Scharf

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L25/04 ,  H05K1/18 ,  H05K3/00

CPC分类号： H01L24/06 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/83 ,  H01L25/04 ,  H05K1/188 ,  H05K3/007 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2224/8019 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15747 ,  H05K2203/0152

摘要： A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

公开(公告)号：US12114433B2

公开(公告)日：2024-10-08

申请号：US17635756

申请日：2020-05-26

申请人： FUJITSU INTERCONNECT TECHNOLOGIES LIMITED

发明人： Hiroshi Nakano ,  Norikazu Ozaki

IPC分类号： H05K3/00 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11 ,  H05K3/04 ,  H05K3/42

CPC分类号： H05K3/0094 ,  H01L23/49827 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/043 ,  H05K3/428

摘要： A substrate that enables increasing an allowable current value of a current path in a thickness direction of the substrate and narrowing spaces between multiple current paths, and the like are provided. To solve this subject, a substrate includes a sheet-shaped first base material (1) having a penetrating hole (1B) in the thickness direction and includes a second base material (2) fitted into the penetrating hole (1B). The second base material (2) includes multiple metal bodies (2B). The metal bodies (2B) penetrate in the thickness direction of the first base material (1) in a state of having an end exposed at each of a first surface and a second surface of the second base material (2) that face each other in the thickness direction.

公开(公告)号：US20240324116A1

公开(公告)日：2024-09-26

申请号：US18499899

申请日：2023-11-01

申请人： Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

发明人： Hayato YAMAGUCHI ,  Masahide TAKAZAWA ,  Shinra YAMANAKA ,  Nobuhiro YAMAMOTO ,  Taichi OKANO

IPC分类号： H05K5/00 ,  H05K1/03 ,  H05K1/05 ,  H05K1/11 ,  H05K3/00

CPC分类号： H05K5/0069 ,  H05K1/0393 ,  H05K1/05 ,  H05K1/116 ,  H05K3/0094 ,  H05K2201/10303

摘要： According to one embodiment, a storage includes a flexible printed circuit board and an electronic component. The flexible printed circuit board includes a first insulating layer, a first conductive layer on a first surface of the first insulating layer, and a second conductive layer on a second surface of the first insulating layer. The second surface is opposite the first surface. The first conductive layer is provided with a land. The second conductive layer covers the land via the first insulating layer in a first direction in which the first surface faces. The electronic component includes a pin joined to the land.

公开(公告)号：US20240324105A1

公开(公告)日：2024-09-26

申请号：US18670986

申请日：2024-05-22

申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA MATERIALS CO., LTD.

发明人： Kentaro IWAI ,  Akito SASAKI

IPC分类号： H05K3/00 ,  H05K1/03 ,  H05K3/46

CPC分类号： H05K3/0044 ,  H05K1/0306 ,  H05K3/4629

摘要： A ceramic substrate for which the yield when forming a notched portion is improved is provided. A ceramic substrate according to an embodiment includes a front surface and a back surface. A notched portion is provided at one or more locations of the ceramic substrate. The notched portion has an opening portion. At least one angle (θ3) where the ceramic substrate is present when viewed from the front surface among angles of end portions of the opening portion is greater than 90 degrees.

公开(公告)号：US20240314940A1

公开(公告)日：2024-09-19

申请号：US18604301

申请日：2024-03-13

申请人： SKYWORKS SOLUTIONS, INC.

发明人： Ki Wook LEE ,  Chien Jen WANG

IPC分类号： H05K3/42 ,  H05K1/11 ,  H05K3/00

CPC分类号： H05K3/429 ,  H05K1/115 ,  H05K3/0047 ,  H05K2201/09518 ,  H05K2201/09545 ,  H05K2203/107

摘要： According to certain aspects, devices and methods can be provided for forming packaging substrates having ringless vias. For instance, a method of forming one or more vias in a packaging substrate can include: laminating a plurality of layers of a packaging substrate; drilling a via hole through the plurality of layers using a through drill, the plurality of layers not including a capture pad or ring along a path of the through drill for drilling the via hole; and forming a via in the via hole using a plating process.

公开(公告)号：US20240312690A1

公开(公告)日：2024-09-19

申请号：US18120761

申请日：2023-03-13

申请人： Intel Corporation

发明人： Ashish SHARMA ,  Arvind SUNDARAM ,  Vikas MISHRA ,  Vimal John CYRIL

IPC分类号： H01F27/28 ,  H01F27/26 ,  H05K1/16 ,  H05K3/00

CPC分类号： H01F27/2804 ,  H01F27/266 ,  H05K1/165 ,  H05K3/005 ,  H01F2027/2809

摘要： Embodiments disclosed herein include a motherboard. In an embodiment, the motherboard comprises a first layer with a first trace with a shape. In an embodiment, an insulating layer is provided over the first layer. In an embodiment, a second layer with a second trace with the shape is over the insulating layer. In an embodiment, the second trace is provided directly over the first trace.

公开(公告)号：US20240306304A1

公开(公告)日：2024-09-12

申请号：US18441334

申请日：2024-02-14

申请人： HYUNDAI MOBIS CO., LTD.

发明人： Chan Yang CHOE ,  Min Ki KIM

IPC分类号： H05K1/18 ,  H01L21/48 ,  H01L23/498 ,  H01L23/64 ,  H05K3/00 ,  H05K3/06

CPC分类号： H05K1/181 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/647 ,  H05K3/0073 ,  H05K3/06 ,  H05K2201/10022 ,  H05K2201/10522 ,  H05K2203/0323 ,  H05K2203/1316

摘要： An apparatus and method for manufacturing a power module is provided. The power module includes: a circuit board having a metal pattern formed thereon; a terminal coupled to the circuit board and electrically connected to at least a portion of the metal pattern; a power device chip bonded to the circuit board and electrically connected to at least a portion of the metal pattern and the terminal; and a molding part covering the power device chip and the circuit board. The circuit board includes: a base part comprising an insulating material; a pattern layer disposed on at least one of an upper surface and a lower surface of the base part and providing the metal pattern; and a thin film resistor having a predetermined circuit pattern connecting the metal patterns disposed on the base part to each other.