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公开(公告)号：US20180331056A1
公开(公告)日：2018-11-15
申请号：US16030973
申请日：2018-07-10
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： CHARLES L. ARVIN , CHRISTOPHER D. MUZZY
IPC: H01L23/00 , H01L23/498 , H01L21/66
CPC classification number: H01L24/06 , H01L22/20 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05113 , H01L2224/05155 , H01L2224/05647 , H01L2224/05666 , H01L2224/0603 , H01L2224/06131 , H01L2224/06132 , H01L2224/06134 , H01L2224/06177 , H01L2224/11001 , H01L2224/1145 , H01L2224/11462 , H01L2224/116 , H01L2224/1161 , H01L2224/13026 , H01L2224/13028 , H01L2224/13078 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13184 , H01L2224/13562 , H01L2224/136 , H01L2224/13639 , H01L2224/16227 , H01L2224/81815 , H01L2924/07025 , H01L2924/014 , H01L2924/00014 , H01L2924/00012
Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.
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公开(公告)号：US09978705B2
公开(公告)日：2018-05-22
申请号：US15222873
申请日：2016-07-28
Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventor： Guo-Cheng Liao , Chia-Ching Chen , Yi-Chuan Ding
CPC classification number: H01L24/16 , H01L21/486 , H01L23/49811 , H01L23/49827 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/32 , H01L24/81 , H01L24/83 , H01L2224/0401 , H01L2224/05025 , H01L2224/08238 , H01L2224/10175 , H01L2224/11436 , H01L2224/11462 , H01L2224/1161 , H01L2224/13008 , H01L2224/13021 , H01L2224/13026 , H01L2224/13027 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2224/13561 , H01L2224/13647 , H01L2224/16012 , H01L2224/16013 , H01L2224/16014 , H01L2224/16105 , H01L2224/16108 , H01L2224/16235 , H01L2224/16503 , H01L2224/32225 , H01L2224/73204 , H01L2224/81139 , H01L2224/81193 , H01L2224/81447 , H01L2224/81815 , H01L2224/83104 , H01L2924/01029 , H01L2924/0105 , H01L2924/014 , H01L2924/3841 , H05K3/007 , H05K3/205 , H05K3/4682 , H05K2201/09509 , H05K2201/10378 , H05K2201/10674 , H01L2924/00014 , H01L2924/00012
Abstract: A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.
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公开(公告)号：US09967982B2
公开(公告)日：2018-05-08
申请号：US13866835
申请日：2013-04-19
Applicant: Palo Alto Research Center Incorporated
Inventor： Eugene M. Chow
IPC: H05K3/32 , H01L21/56 , H01L21/683 , H01L23/31 , H01L23/48 , H01L23/498 , H01L23/00 , G01R1/067
CPC classification number: H05K3/32 , G01R1/06727 , H01L21/56 , H01L21/6835 , H01L23/3157 , H01L23/48 , H01L23/49811 , H01L24/13 , H01L24/16 , H01L24/72 , H01L24/73 , H01L2221/68331 , H01L2221/68377 , H01L2221/68381 , H01L2224/1161 , H01L2224/1182 , H01L2224/1191 , H01L2224/13008 , H01L2224/13012 , H01L2224/13016 , H01L2224/13022 , H01L2224/13026 , H01L2224/131 , H01L2224/1355 , H01L2224/13564 , H01L2224/136 , H01L2224/16225 , H01L2224/48091 , H01L2224/81192 , H01L2224/81801 , H01L2224/819 , H01L2924/0001 , H01L2924/01006 , H01L2924/01012 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01042 , H01L2924/01074 , H01L2924/01082 , H01L2924/01093 , H01L2924/014 , H01L2924/14 , H05K3/281 , H05K3/4007 , H05K3/4092 , H05K2201/10378 , Y10T29/49124 , Y10T29/49147 , H01L2924/00014 , H01L2924/00 , H01L2224/13099
Abstract: An interposer including stress-engineered nonplanar microsprings may provide interconnection of bonding pads of electronic structures disposed above and below the interposer. The lateral offset between an anchor portion of a microspring disposed for contact at a bottom surface of the interposer and the tip of the microspring located in a free portion of the microspring for contact and deflection over a top surface of the interposer permits the interconnection of devices having different bonding pad pitches. Microspring contacts at the free portion permit temporary interconnection of devices, while solder applied over the free portion permit permanent connection of devices to the interposer.
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公开(公告)号：US09799618B1
公开(公告)日：2017-10-24
申请号：US15291767
申请日：2016-10-12
Applicant: International Business Machines Corporation
Inventor： Charles L. Arvin , Christopher D. Muzzy
IPC: H01L23/498 , H01L23/00 , H01L21/66
CPC classification number: H01L24/06 , H01L22/20 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05113 , H01L2224/05155 , H01L2224/05647 , H01L2224/05666 , H01L2224/0603 , H01L2224/06131 , H01L2224/06132 , H01L2224/06134 , H01L2224/06177 , H01L2224/11001 , H01L2224/1145 , H01L2224/11462 , H01L2224/116 , H01L2224/1161 , H01L2224/13026 , H01L2224/13028 , H01L2224/13078 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13184 , H01L2224/13562 , H01L2224/136 , H01L2224/13639 , H01L2224/16227 , H01L2224/81815 , H01L2924/07025 , H01L2924/014 , H01L2924/00014 , H01L2924/00012
Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.
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公开(公告)号：US20170278814A1
公开(公告)日：2017-09-28
申请号：US15076831
申请日：2016-03-22
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor： Chih-Pin HUNG , Dao-Long CHEN , Ying-Ta CHIU , Ping-Feng YANG
IPC: H01L23/00
CPC classification number: H01L24/13 , H01L24/05 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/1161 , H01L2224/11622 , H01L2224/13012 , H01L2224/13015 , H01L2224/13017 , H01L2224/13018 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/16145 , H01L2224/16227 , H01L2224/81385 , H01L2224/81815 , H01L2924/00012 , H01L2924/014 , H01L2924/00014
Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.
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公开(公告)号：US09741693B2
公开(公告)日：2017-08-22
申请号：US14939253
申请日：2015-11-12
Inventor： Chin-Fu Kao , Tsei-Chung Fu , Jing-Cheng Lin
IPC: H01L25/065 , H01L25/00
CPC classification number: H01L25/0657 , H01L21/76898 , H01L24/05 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/80 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/50 , H01L2224/04 , H01L2224/0401 , H01L2224/05557 , H01L2224/05638 , H01L2224/05647 , H01L2224/05687 , H01L2224/0569 , H01L2224/08145 , H01L2224/1161 , H01L2224/11616 , H01L2224/11831 , H01L2224/13009 , H01L2224/13019 , H01L2224/13124 , H01L2224/13147 , H01L2224/13184 , H01L2224/1601 , H01L2224/16012 , H01L2224/16145 , H01L2224/16146 , H01L2224/2919 , H01L2224/32145 , H01L2224/73201 , H01L2224/73204 , H01L2224/80075 , H01L2224/80203 , H01L2224/80896 , H01L2224/8101 , H01L2224/81011 , H01L2224/81012 , H01L2224/81022 , H01L2224/81075 , H01L2224/81203 , H01L2224/81895 , H01L2224/83075 , H01L2224/83104 , H01L2224/83191 , H01L2224/83203 , H01L2224/9211 , H01L2224/94 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565 , H01L2924/1434 , H01L2924/3511 , H01L2224/81 , H01L2924/01014 , H01L2924/05442 , H01L2924/05042 , H01L2924/00014 , H01L2924/07025 , H01L2224/83 , H01L2224/80 , H01L2924/00012 , H01L2224/08 , H01L2224/16 , H01L2924/01029 , H01L2924/00
Abstract: The present disclosure provides a semiconductor package, including a first device having a first joining surface, a first conductive component at least partially protruding from the first joining surface, a second device having a second joining surface facing the first joining surface, and a second conductive component at least exposing from the second joining surface. The first conductive component and the second conductive component form a joint having a first beak. The first beak points to either the first joining surface or the second joining surface.
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公开(公告)号：US20160128206A9
公开(公告)日：2016-05-05
申请号：US13866835
申请日：2013-04-19
Applicant: Palo Alto Research Center Incorporated
Inventor： Eugene M. Chow
IPC: H05K3/32
CPC classification number: H05K3/32 , G01R1/06727 , H01L21/56 , H01L21/6835 , H01L23/3157 , H01L23/48 , H01L23/49811 , H01L24/13 , H01L24/16 , H01L24/72 , H01L24/73 , H01L2221/68331 , H01L2221/68377 , H01L2221/68381 , H01L2224/1161 , H01L2224/1182 , H01L2224/1191 , H01L2224/13008 , H01L2224/13012 , H01L2224/13016 , H01L2224/13022 , H01L2224/13026 , H01L2224/131 , H01L2224/1355 , H01L2224/13564 , H01L2224/136 , H01L2224/16225 , H01L2224/48091 , H01L2224/81192 , H01L2224/81801 , H01L2224/819 , H01L2924/0001 , H01L2924/01006 , H01L2924/01012 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01042 , H01L2924/01074 , H01L2924/01082 , H01L2924/01093 , H01L2924/014 , H01L2924/14 , H05K3/281 , H05K3/4007 , H05K3/4092 , H05K2201/10378 , Y10T29/49124 , Y10T29/49147 , H01L2924/00014 , H01L2924/00 , H01L2224/13099
Abstract: An interposer including stress-engineered nonplanar microsprings may provide interconnection of bonding pads of electronic structures disposed above and below the interposer. The lateral offset between an anchor portion of a microspring disposed for contact at a bottom surface of the interposer and the tip of the microspring located in a free portion of the microspring for contact and deflection over a top surface of the interposer permits the interconnection of devices having different bonding pad pitches. Microspring contacts at the free portion permit temporary interconnection of devices, while solder applied over the free portion permit permanent connection of devices to the interposer.
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公开(公告)号：US20150294928A1
公开(公告)日：2015-10-15
申请号：US14669169
申请日：2015-03-26
Applicant: ROHM CO., LTD.
Inventor： Kenji FUJII , Yasumasa KASUYA , Mamoru YAMAGAMI , Naoki KINOSHITA , Motoharu HAGA
IPC: H01L23/495 , H01L23/00 , H01L23/367 , H01L23/31 , H01L23/29
CPC classification number: H01L23/49527 , H01L23/291 , H01L23/293 , H01L23/3107 , H01L23/3114 , H01L23/3142 , H01L23/3171 , H01L23/3675 , H01L23/4334 , H01L23/4822 , H01L23/49503 , H01L23/49548 , H01L23/49551 , H01L23/49568 , H01L23/49572 , H01L23/525 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/33 , H01L24/73 , H01L24/75 , H01L24/81 , H01L24/83 , H01L2224/02311 , H01L2224/02331 , H01L2224/0239 , H01L2224/024 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/03462 , H01L2224/0401 , H01L2224/05008 , H01L2224/05073 , H01L2224/05082 , H01L2224/05083 , H01L2224/05084 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05181 , H01L2224/05548 , H01L2224/05567 , H01L2224/05572 , H01L2224/05582 , H01L2224/05583 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05681 , H01L2224/05684 , H01L2224/1145 , H01L2224/1146 , H01L2224/1147 , H01L2224/1161 , H01L2224/11825 , H01L2224/13008 , H01L2224/13011 , H01L2224/13016 , H01L2224/13017 , H01L2224/13019 , H01L2224/13024 , H01L2224/13147 , H01L2224/13561 , H01L2224/13582 , H01L2224/13624 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2224/13664 , H01L2224/13666 , H01L2224/16014 , H01L2224/16245 , H01L2224/16258 , H01L2224/17107 , H01L2224/29008 , H01L2224/29082 , H01L2224/29124 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29164 , H01L2224/29166 , H01L2224/32245 , H01L2224/73253 , H01L2224/753 , H01L2224/75301 , H01L2224/75981 , H01L2224/81191 , H01L2224/81192 , H01L2224/81201 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/8146 , H01L2224/81464 , H01L2224/81466 , H01L2224/8183 , H01L2224/83191 , H01L2224/83201 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/8346 , H01L2224/83464 , H01L2224/83466 , H01L2224/8383 , H01L2224/92225 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/05042 , H01L2924/07025 , H01L2924/17724 , H01L2924/17747 , H01L2924/181 , H01L2924/182 , H01L2924/186 , H01L2924/00012 , H01L2924/00014 , H01L2224/05166 , H01L2924/01028 , H01L2924/0665
Abstract: A semiconductor device has a semiconductor element provided with a functional surface on which a functional circuit is formed and with a back surface facing in the opposite direction to the functional surface, while also having a lead supporting the semiconductor element and electrically connected to the semiconductor element, and a resin package covering at least a portion of the semiconductor element and the lead. The semiconductor element has a functional surface side electrode formed on the functional surface and equipped with a functional surface side raised part that projects in the direction in which the functional surface faces. The functional surface side raised part of the functional surface side electrode is joined to the lead by solid state bonding.
Abstract translation: 半导体器件具有设置有功能表面的半导体元件，功能电路形成在其上，并且背面面向与功能表面相反的方向，同时还具有支撑半导体元件并与半导体元件电连接的引线 以及覆盖半导体元件和引线的至少一部分的树脂封装。 半导体元件具有形成在功能面上的功能面侧电极，其具有在功能面朝向的方向突出的功能面侧凸起部。 功能面侧电极的功能面侧隆起部通过固态接合而与引线接合。
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公开(公告)号：US20150194402A1
公开(公告)日：2015-07-09
申请号：US14662295
申请日：2015-03-19
Inventor： Chun-Lei HSU , Ming-Che HO , Ming-Da CHENG , Chung-Shi LIU
IPC: H01L23/00
CPC classification number: H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/03424 , H01L2224/03464 , H01L2224/0347 , H01L2224/0401 , H01L2224/05559 , H01L2224/05571 , H01L2224/05572 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/1148 , H01L2224/1161 , H01L2224/11616 , H01L2224/11831 , H01L2224/13005 , H01L2224/13022 , H01L2224/1308 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13169 , H01L2924/00013 , H01L2924/0002 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/00014 , H01L2924/01014 , H01L2924/206 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552
Abstract: A method of forming a semiconductor device includes forming an under-bump metallurgy (UBM) layer overlying a portion of a metal pad region within an opening of an encapsulating layer over a semiconductor substrate, and forming a bump layer overlying the UBM layer to fill the opening of the encapsulating layer. A removal process is initiated on an upper surface of the encapsulating layer and a coplanar top surface of the bump layer to remove the upper surface of the encapsulating layer until a top portion of the bump layer protrudes from the encapsulating layer.
Abstract translation: 一种形成半导体器件的方法包括在半导体衬底上形成覆盖在封装层的开口内的金属焊盘区域的一部分上的凸块下金属（UBM）层，以及形成覆盖在UBM层上的凸块层，以填充 打开封装层。 在封装层的上表面和凸起层的共面顶表面上开始去除工艺，以去除封装层的上表面，直到凸起层的顶部从封装层突出。
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公开(公告)号：US08866293B2
公开(公告)日：2014-10-21
申请号：US13167086
申请日：2011-06-23
Applicant: Yi-Hung Lin , Meng-Tsung Lee , Sui-An Kao , Yi-Hsin Chen , Feng-Lung Chien
Inventor： Yi-Hung Lin , Meng-Tsung Lee , Sui-An Kao , Yi-Hsin Chen , Feng-Lung Chien
CPC classification number: H01L24/11 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0345 , H01L2224/0361 , H01L2224/03622 , H01L2224/039 , H01L2224/03901 , H01L2224/03903 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05166 , H01L2224/0556 , H01L2224/05564 , H01L2224/05572 , H01L2224/05647 , H01L2224/11462 , H01L2224/116 , H01L2224/11849 , H01L2224/119 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/01022 , H01L2924/01029 , H01L2924/0132 , H01L2924/01074 , H01L2924/014 , H01L2224/0347 , H01L2224/1161 , H01L2224/05552
Abstract: A semiconductor structure includes a semiconductor chip having at least an electrode pad, a first metal layer formed on the electrode pad, a second metal layer completely formed on and in contact with the first metal layer, and a conductive pillar disposed on the second metal layer, where a material of the first metal layer is different from a material of the second metal layer, the first metal layer has a first distribution-projected area larger than a second distribution projected-area of the conductive pillar, and the second metal layer has a third distribution-projected area that is the same as the second distribution-projected area of the conductive pillar.
Abstract translation: 半导体结构包括具有至少电极焊盘，形成在电极焊盘上的第一金属层，完全形成在第一金属层上并与第一金属层接触的第二金属层的半导体芯片和设置在第二金属层上的导电柱 其中，所述第一金属层的材料与所述第二金属层的材料不同，所述第一金属层具有大于所述导电柱的第二分布投影面积的第一分布投影面积，并且所述第二金属层具有 与导电柱的第二分布投影面积相同的第三分布投影面积。
