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公开(公告)号：US20240355728A1
公开(公告)日：2024-10-24
申请号：US18451263
申请日：2023-08-17
发明人： Kai-Chun Chang , Hsieh-Hung Hsieh , Tzu-Jin Yeh , Ching-Chung Hsu , Chung-Long Chang , Hua-Chou Tseng
IPC分类号： H01L23/522 , H01L23/00 , H01L23/528 , H01L23/532
CPC分类号： H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/53219 , H01L23/53233 , H01L24/05 , H01L24/13 , H01L2224/02313 , H01L2224/02331 , H01L2224/0235 , H01L2224/02373 , H01L2224/02375 , H01L2224/02381 , H01L2224/0239 , H01L2224/05548 , H01L2224/05557 , H01L2224/13007 , H01L2924/30107
摘要： A semiconductor structure includes a circuit with a redistribution layer (RDL) formed over the circuit. The redistribution layer comprises a plurality of metal layers. An inductor is formed in a topmost metal layer, and the circuit is located directly under the inductor. An under bump metallization (UBM) layer formed on the topmost metal layer and a conductive connector formed on the UBM layer.
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公开(公告)号：US12074096B2
公开(公告)日：2024-08-27
申请号：US16793887
申请日：2020-02-18
IPC分类号： H01L23/495 , H01L21/683 , H01L23/00 , H01L23/36 , H01L23/49 , H01L23/492 , H01L23/532
CPC分类号： H01L23/49517 , H01L23/49 , H01L23/492 , H01L23/49513 , H01L23/49524 , H01L23/49562 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/08 , H01L2224/0401 , H01L2224/04026 , H01L2224/04042 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05568 , H01L2224/05647 , H01L2224/13007 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16245 , H01L2224/291 , H01L2224/32245 , H01L2224/73253 , H01L2224/73265 , H01L2224/81815 , H01L2224/92247 , H01L2224/94 , H01L2224/94 , H01L2224/03 , H01L2224/94 , H01L2224/11 , H01L2224/13147 , H01L2924/00014 , H01L2224/131 , H01L2924/013 , H01L2924/00014 , H01L2224/05166 , H01L2924/00014 , H01L2224/05155 , H01L2924/00014 , H01L2224/05171 , H01L2924/00014 , H01L2224/05647 , H01L2924/00014 , H01L2224/291 , H01L2924/013 , H01L2924/00014
摘要： A microelectronic device is formed by thinning a substrate of the microelectronic device from a die attach surface of the substrate, and forming a copper-containing layer on the die attach surface of the substrate. A protective metal layer is formed on the copper-containing layer. Subsequently, the copper-containing layer is attached to a package member having a package die mount area. The protective metal layer may optionally be removed prior to attaching the copper-containing layer to the package member. Alternatively, the protective metal layer may be left on the copper-containing layer when the copper-containing layer is attached to the package member. A structure formed by the method is also disclosed.
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公开(公告)号：US20240222303A1
公开(公告)日：2024-07-04
申请号：US18226589
申请日：2023-07-26
发明人： Daehyun KIM , KUNSIL LEE
IPC分类号： H01L23/00 , H01L23/498
CPC分类号： H01L24/14 , H01L23/49811 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/11 , H01L24/17 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/81 , H01L25/18 , H01L2224/05073 , H01L2224/05144 , H01L2224/05555 , H01L2224/0557 , H01L2224/05573 , H01L2224/05647 , H01L2224/0603 , H01L2224/06051 , H01L2224/0613 , H01L2224/06181 , H01L2224/08145 , H01L2224/08225 , H01L2224/1146 , H01L2224/11849 , H01L2224/13007 , H01L2224/13013 , H01L2224/13014 , H01L2224/13111 , H01L2224/13147 , H01L2224/1403 , H01L2224/14051 , H01L2224/1413 , H01L2224/16105 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253 , H01L2224/81815
摘要： Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first substrate having first pads on a first surface of the first substrate, a second substrate on the first substrate and having a plurality of second pads on a second surface of the second substrate, and connection terminals between the first substrate and the second substrate and correspondingly coupling the first pad to the second pads. Each of the connection terminals has a first major axis and a first minor axis that are parallel to the first surface of the first substrate and are orthogonal to each other. When viewed in a plan view, the first minor axis of each of the connection terminals is directed toward a center of the first substrate.
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公开(公告)号：US20240203833A1
公开(公告)日：2024-06-20
申请号：US18541254
申请日：2023-12-15
发明人： Jungil SON , Taeyoon KIM , Kunwoo KU , Sungwook MOON
IPC分类号： H01L23/48 , H01L21/768 , H01L23/00 , H01L23/522
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/5226 , H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/0557 , H01L2224/06181 , H01L2224/13007
摘要： The present disclosure provides a semiconductor chip. In some embodiments, a semiconductor chip includes a semiconductor substrate, an integrated circuit layer formed on the semiconductor substrate, and a plurality of metal wiring layers sequentially formed on the semiconductor substrate and the integrated circuit layer. The semiconductor chip further includes a first through via structure bundle extending in a vertical direction from a first metal wiring layer of the plurality of metal wiring layers toward the semiconductor substrate and penetrating through the semiconductor substrate. The semiconductor chip further includes a second through via structure bundle spaced apart from the first through via structure bundle, extending in the vertical direction from a second metal wiring layer of the plurality of metal wiring layers toward the semiconductor substrate, and penetrating through the semiconductor substrate.
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公开(公告)号：US20240186248A1
公开(公告)日：2024-06-06
申请号：US18523131
申请日：2023-11-29
发明人： Belgacem HABA , Cyprian Emeka UZOH , Rajesh KATKAR
IPC分类号： H01L23/528 , H01L23/00 , H01L23/367 , H01L23/498 , H01L25/065
CPC分类号： H01L23/5286 , H01L23/3672 , H01L23/49816 , H01L23/49822 , H01L24/05 , H01L24/13 , H01L25/0657 , H01L2224/05009 , H01L2224/05025 , H01L2224/13007 , H01L2224/13026 , H01L2225/06513 , H01L2225/06527 , H01L2924/01029 , H01L2924/1427 , H01L2924/1431 , H01L2924/15311
摘要： An assembly may include a reconstituted element having a front surface and a back surface, the reconstituted element comprising: a semiconductor die having a front side and a back side, the semiconductor die including circuitry closer to the front side than to the back side and a via extending from the back side of the semiconductor die to connect to the circuitry, an insulating material disposed along a side surface of the semiconductor die, a power rail extending from the front surface to the back surface of the reconstituted element and configured to deliver power to the semiconductor die; and an interconnect structure configured to electrically connect the power rail to the via and to deliver power to the semiconductor die from the back side of the semiconductor die.
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公开(公告)号：US20240087967A1
公开(公告)日：2024-03-14
申请号：US18513649
申请日：2023-11-20
IPC分类号： H01L21/66 , H01L23/00 , H01L23/31 , H01L23/498
CPC分类号： H01L22/32 , H01L23/3157 , H01L23/49822 , H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/0217 , H01L2224/0401 , H01L2224/05556 , H01L2224/06515 , H01L2224/13007
摘要： An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.
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公开(公告)号：US11894353B2
公开(公告)日：2024-02-06
申请号：US17010575
申请日：2020-09-02
发明人： Zhiwei Liang , Wenqian Luo , Guoqiang Wang , Yingwei Liu
CPC分类号： H01L25/167 , H01L24/03 , H01L24/11 , H01L24/13 , H01L24/81 , H01L27/124 , H01L27/1259 , H01L2224/0382 , H01L2224/10122 , H01L2224/1182 , H01L2224/13007 , H01L2224/13016 , H01L2224/13078 , H01L2224/81201
摘要： The present disclosure provides a driving substrate and a manufacturing method thereof, and a micro LED bonding method. The driving substrate includes: a base substrate; a driving function layer provided on the base substrate, and including a plurality of driving thin film transistors and a plurality of common electrode lines; a pad layer including a plurality of pads provided on a side of the driving function layer away from the base substrate, each pad including a pad body and a microstructure of hard conductive material provided on a side of the pad body away from the base substrate; and a plurality of buffer structures provided on the side of the driving function layer away from the base substrate, each buffer structure surrounding a portion of a corresponding microstructure close to the base substrate, and a height of the buffer structure being lower than a height of the microstructure.
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公开(公告)号：US20240030145A1
公开(公告)日：2024-01-25
申请号：US18109392
申请日：2023-02-14
发明人： Myungsam KANG
IPC分类号： H01L23/538 , H10B80/00 , H01L23/00 , H01L21/48
CPC分类号： H01L23/5385 , H10B80/00 , H01L23/5386 , H01L24/13 , H01L24/14 , H01L24/16 , H01L21/4853 , H01L24/11 , H01L2224/13147 , H01L2224/13007 , H01L2224/13562 , H01L2224/1357 , H01L2224/13655 , H01L2224/13644 , H01L2224/16227 , H01L2924/1461 , H01L2924/1438 , H01L2924/14361 , H01L2924/1437 , H01L2924/1443 , H01L2924/14511 , H01L2224/11825
摘要： A semiconductor package includes a connection substrate with a cavity, a first semiconductor chip and a second semiconductor chip on the connection substrate, a third semiconductor chip in the cavity of the connection substrate, the first semiconductor chip and the second semiconductor chip being on the third semiconductor chip and being connected to each other through the third semiconductor chip, and a molding layer that covers the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip, wherein the third semiconductor chip includes first bumps that are exposed through the molding layer and are connected to the first semiconductor chip and the second semiconductor chip.
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公开(公告)号：US11869819B2
公开(公告)日：2024-01-09
申请号：US17870871
申请日：2022-07-22
IPC分类号： H01L21/66 , H01L23/498 , H01L23/31 , H01L23/00
CPC分类号： H01L22/32 , H01L23/3157 , H01L23/49822 , H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/0217 , H01L2224/0401 , H01L2224/05556 , H01L2224/06515 , H01L2224/13007
摘要： An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.
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10.发明公开公开(公告)号：US20240006360A1
公开(公告)日：2024-01-04
申请号：US17853978
申请日：2022-06-30
发明人： Hsih-Yang CHIU
IPC分类号： H01L23/00
CPC分类号： H01L24/13 , H01L24/16 , H01L24/11 , H01L24/81 , H01L2224/16148 , H01L2224/81203 , H01L2224/11622 , H01L2224/11462 , H01L2224/13147 , H01L2224/13007 , H01L2224/13541 , H01L2224/13553 , H01L2224/13561 , H01L2224/1358 , H01L2224/13687 , H01L24/05 , H01L2224/05624 , H01L2224/05555 , H01L2224/13666 , H01L2224/13647 , H01L2224/13611 , H01L2224/13639 , H01L2224/13014 , H01L2924/3841
摘要： The present application provides a semiconductor structure having a copper pillar within a solder bump, and a manufacturing method of the semiconductor structure. The semiconductor structure includes a substrate having a pad disposed thereon and a passivation at least partially surrounding the pad; and a conductive bump structure disposed over the passivation and the pad, wherein the conductive bump structure includes a first bump portion disposed over the passivation and the pad, a conductive pillar disposed over the first bump portion, and a second bump portion disposed over and surrounding the conductive pillar.
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