公开(公告)号：US20240203833A1

公开(公告)日：2024-06-20

申请号：US18541254

申请日：2023-12-15

申请人： SAMSUNG ELECTRONICS CO., LTD

发明人： Jungil SON ,  Taeyoon KIM ,  Kunwoo KU ,  Sungwook MOON

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13007

摘要： The present disclosure provides a semiconductor chip. In some embodiments, a semiconductor chip includes a semiconductor substrate, an integrated circuit layer formed on the semiconductor substrate, and a plurality of metal wiring layers sequentially formed on the semiconductor substrate and the integrated circuit layer. The semiconductor chip further includes a first through via structure bundle extending in a vertical direction from a first metal wiring layer of the plurality of metal wiring layers toward the semiconductor substrate and penetrating through the semiconductor substrate. The semiconductor chip further includes a second through via structure bundle spaced apart from the first through via structure bundle, extending in the vertical direction from a second metal wiring layer of the plurality of metal wiring layers toward the semiconductor substrate, and penetrating through the semiconductor substrate.

公开(公告)号：US20230154866A1

公开(公告)日：2023-05-18

申请号：US17875639

申请日：2022-07-28

申请人： SAMSUNG ELECTRONICS CO., LTD

发明人： Juyoun CHOI ,  Miyeon KIM ,  Jungil SON

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/498

CPC分类号： H01L23/562 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/14 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2224/14517 ,  H01L2924/1205 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/3511

摘要： A semiconductor package includes a package base substrate including a potential plate. An interposer is arranged on the package base substrate and comprises at least one interposer through electrode, at least one first connection bump, and at least one second connection bump. A first stacked chip unit is arranged on the interposer and comprises a first semiconductor chip and at least one second semiconductor chips arranged on the first semiconductor chip. At least one passive device unit is arranged on the package base substrate. The at least one passive device unit is spaced apart from the interposer in a horizontal direction parallel to an upper surface of the package base substrate. The at least one first connection bump is a dummy bump. The potential plate electrically connects the at least one first connection bump and a power terminal of the at least one passive device unit to each other.