公开(公告)号：US20240203833A1

公开(公告)日：2024-06-20

申请号：US18541254

申请日：2023-12-15

申请人： SAMSUNG ELECTRONICS CO., LTD

发明人： Jungil SON ,  Taeyoon KIM ,  Kunwoo KU ,  Sungwook MOON

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13007

摘要： The present disclosure provides a semiconductor chip. In some embodiments, a semiconductor chip includes a semiconductor substrate, an integrated circuit layer formed on the semiconductor substrate, and a plurality of metal wiring layers sequentially formed on the semiconductor substrate and the integrated circuit layer. The semiconductor chip further includes a first through via structure bundle extending in a vertical direction from a first metal wiring layer of the plurality of metal wiring layers toward the semiconductor substrate and penetrating through the semiconductor substrate. The semiconductor chip further includes a second through via structure bundle spaced apart from the first through via structure bundle, extending in the vertical direction from a second metal wiring layer of the plurality of metal wiring layers toward the semiconductor substrate, and penetrating through the semiconductor substrate.

公开(公告)号：US20240258275A1

公开(公告)日：2024-08-01

申请号：US18420210

申请日：2024-01-23

申请人： SAMSUNG ELECTRONICS CO.,LTD.

发明人： Duhyoung AHN ,  Minseok KANG ,  Sungwook MOON

IPC分类号： H01L25/065 ,  H01L21/66 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L24/16 ,  H01L22/32 ,  H01L2224/16148 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/381

摘要： A semiconductor package includes a first semiconductor chip, a second semiconductor chip stacked on the first semiconductor chip, and a plurality of external connection terminals electrically coupled to a lower surface of the first semiconductor chip. The first semiconductor chip includes a substrate including the lower surface and an opposite upper surface, a lower wiring layer in a lower portion of the lower surface including a first plurality of wiring patterns, an upper wiring layer in an upper portion of the upper surface including a second plurality of wiring patterns, a plurality of through structures electrically coupling the lower wiring layer to the upper wiring layer and penetrating the substrate, and a macro cell disposed between the plurality of through structures. At least one of the through structures partially overlaps a wiring pattern of the lower wiring layer in a vertical direction within an overlapping distance from the wiring pattern.

公开(公告)号：US20200320243A1

公开(公告)日：2020-10-08

申请号：US16835423

申请日：2020-03-31

申请人： Samsung Electronics Co., Ltd.

发明人： Yoonjae HWANG ,  Sungwook MOON

IPC分类号： G06F30/392 ,  H01L23/498 ,  H01L23/522 ,  H01L21/48 ,  H01L25/065 ,  H01L25/00 ,  G06F30/373

摘要： A design method for a semiconductor package including a first chip, a second chip, a 2.5 dimensional (2.5D) interposer, a package substrate, and a board includes generating a layout including the 2.5D interposer on the package substrate and the first and second chips individually arranged on the 2.5D interposer, based on design information; analyzing signal integrity and power integrity between the first and second chips from the layout; analyzing signal integrity or power integrity between the first chip and at least one third chip on the board from the layout; and determining whether to modify the layout based on the analysis results.

公开(公告)号：US20240105650A1

公开(公告)日：2024-03-28

申请号：US18213470

申请日：2023-06-23

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Duhyoung AHN ,  Minseok KANG ,  Sungwook MOON ,  Yongjin HONG

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

CPC分类号： H01L24/06 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/06177 ,  H01L2224/06515 ,  H01L2224/16145 ,  H01L2225/06513

摘要： Provided is a semiconductor package including a three-dimensional (3D) stacked structure in which an upper second semiconductor chip is stacked on a lower first semiconductor chip. In the semiconductor package, a power distribution network for the first semiconductor chip and a power distribution network for the second semiconductor chip are implemented through circuits of the first semiconductor chip and separated from the first semiconductor chip.