公开(公告)号：US09824944B2

公开(公告)日：2017-11-21

申请号：US15280618

申请日：2016-09-29

申请人： Renesas Electronics Corporation

发明人： Bunji Yasumura ,  Fumio Tsuchiya ,  Hisanori Ito ,  Takuji Ide ,  Naoki Kawanabe ,  Masanao Sato

IPC分类号： H01L21/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L22/32 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/0613 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/30107 ,  H01L2924/3512 ,  H01L2924/00

摘要： A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.

公开(公告)号：US20150294962A1

公开(公告)日：2015-10-15

申请号：US14730030

申请日：2015-06-03

申请人： STATS ChipPAC, Ltd.

发明人： Yaojian Lin ,  Kang Chen

IPC分类号： H01L25/00 ,  H01L23/00 ,  H01L25/07

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/04 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/03002 ,  H01L2224/03003 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/0613 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14104 ,  H01L2224/16111 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/24137 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/82005 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2224/11 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/13015 ,  H01L2224/81

摘要： A semiconductor device has a temporary carrier. A semiconductor die is oriented with an active surface toward, and mounted to, the temporary carrier. An encapsulant is deposited with a first surface over the temporary carrier and a second surface, opposite the first surface, is deposited over a backside of the semiconductor die. The temporary carrier is removed. A portion of the encapsulant in a periphery of the semiconductor die is removed to form an opening in the first surface of the encapsulant. An interconnect structure is formed over the active surface of the semiconductor die and extends into the opening in the encapsulant layer. A via is formed and extends from the second surface of the encapsulant to the opening. A first bump is formed in the via and electrically connects to the interconnect structure.

摘要翻译： 半导体器件具有临时载体。 半导体管芯被定向成具有朝着临时载体并且安装到临时载体的有源表面。 密封剂在临时载体上沉积有第一表面，并且与第一表面相对的第二表面沉积在半导体管芯的背面上。 移除临时载体。 去除半导体管芯的周边中的密封剂的一部分，以在密封剂的第一表面中形成开口。 互连结构形成在半导体管芯的有源表面上并延伸到密封剂层中的开口中。 通孔形成并从密封剂的第二表面延伸到开口。 在通孔中形成第一凸起并且电连接到互连结构。

公开(公告)号：US20150130049A1

公开(公告)日：2015-05-14

申请号：US14077019

申请日：2013-11-11

申请人： Taiwan Semiconductor Manufacturing Company Ltd.

发明人： YING-JU CHEN ,  HSIEN-WEI CHEN

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L24/05 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05088 ,  H01L2224/05092 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05684 ,  H01L2224/0613 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/16111 ,  H01L2224/16145 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

摘要： A semiconductor device includes a carrier and a metallic structure including a metallic member, a pad and a via portion; wherein the metallic member is disposed inside the carrier, the pad is configured for receiving a solder bump and is disposed on a surface of the carrier, the via portion is configured for electrically connecting the metallic member and the pad, and the via portion is disposed proximal to an end of the pad. Further, a method of manufacturing a semiconductor device includes providing a carrier, removing a portion of the carrier for forming a via extending a surface of the carrier to an interior of the carrier, filling the via by a conductive material, and disposing the conductive material on the surface of the carrier, wherein the via is disposed proximal to an end portion of the conductive material.

摘要翻译： 半导体器件包括载体和包括金属部件，焊盘和通孔部分的金属结构; 其特征在于，所述金属部件配置在所述载体的内部，所述焊盘被构造成用于容纳焊料凸块并且设置在所述载体的表面上，所述通孔部分被构造用于电连接所述金属部件和所述焊盘，并且所述通孔部分被设置 靠近垫的一端。 此外，制造半导体器件的方法包括提供载体，去除用于形成载体的表面的载体的一部分，以将载体的表面延伸到载体的内部，用导电材料填充该通孔，并且将导电材料 在载体的表面上，其中通孔设置在导电材料的端部附近。

公开(公告)号：US08946705B2

公开(公告)日：2015-02-03

申请号：US12778123

申请日：2010-05-12

申请人： Bunji Yasumura ,  Fumio Tsuchiya ,  Hisanori Ito ,  Takuji Ide ,  Naoki Kawanabe ,  Masanao Sato

发明人： Bunji Yasumura ,  Fumio Tsuchiya ,  Hisanori Ito ,  Takuji Ide ,  Naoki Kawanabe ,  Masanao Sato

IPC分类号： H01L23/58 ,  H01L29/10 ,  H01L23/48 ,  H01L23/52 ,  H01L23/00

CPC分类号： H01L22/32 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/0613 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/30107 ,  H01L2924/3512 ,  H01L2924/00

摘要： A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.

摘要翻译： 提供了能够防止半导体装置的最上层的保护膜的破裂的技术，提高了半导体装置的可靠性。 在半导体芯片的主表面上形成的接合焊盘为矩形，并且在每个接合焊盘上的保护膜中形成开口，使得保护膜在每个接合的引线接合区域中的重叠宽度 衬垫比每个焊盘的探针区域中的保护膜的重叠宽度宽。

公开(公告)号：US08461697B2

公开(公告)日：2013-06-11

申请号：US13224649

申请日：2011-09-02

申请人： Mitsushi Nozoe

发明人： Mitsushi Nozoe

IPC分类号： H01L23/48

CPC分类号： H01L24/06 ,  H01L23/5286 ,  H01L2224/05553 ,  H01L2224/0613 ,  H01L2224/06515 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01082 ,  H01L2924/14

摘要： In a semiconductor integrated circuit device, arrangement relationship of power source area I/O pads differs between a peripheral portion and a center portion of a gate region of a chip. That is, in two columns and two rows of the peripheral portion of the gate region, VDD area I/O pads connected to a high-voltage power source VDD and GND area I/O pads connected to a ground power source GND are alternately aligned and arranged both in a row direction and in a column direction. Moreover, in the center portion of the gate region, the same VDD area I/O pads or the same GND area I/O pads are successively aligned in the row direction, and the VDD area I/O pads and the GND area I/O pads are alternately aligned and arranged in the column direction.

摘要翻译： 在半导体集成电路器件中，电源区域I / O焊盘的配置关系在芯片的栅极区域的周边部分和中心部分之间不同。 也就是说，在栅极区域的周边部分的两列和两行中，连接到高压电源VDD的VDD区域I / O焊盘和连接到地电源GND的GND区域I / O焊盘交替对准 并且在行方向和列方向上布置。 此外，在栅极区域的中心部分，相同的VDD区域I / O焊盘或相同的GND区域I / O焊盘在行方向上连续对准，并且VDD区域I / O焊盘和GND区域I / O焊盘在列方向上交替排列并排列。

公开(公告)号：US11990464B2

公开(公告)日：2024-05-21

申请号：US17204797

申请日：2021-03-17

申请人： SOCIONEXT INC.

发明人： Toru Matsui

IPC分类号： H01L27/02 ,  H01L27/11 ,  H01L27/118

CPC分类号： H01L27/0207 ,  H01L27/11898 ,  H01L2224/0613 ,  H01L2224/06134 ,  H01L2224/0616 ,  H01L2224/06163 ,  H01L2224/06177

摘要： Provided is a semiconductor integrated circuit device including a plurality of columns of IO cells and having a configuration capable of reducing wiring delays without causing an increase in the area. The semiconductor integrated circuit device includes a first IO cell column group including an IO cell column closest to a periphery of a chip, and a second IO cell column group including an IO cell column adjacent to the first IO cell column group at the side closer to the core region. At least one of the first IO cell column group or the second IO cell column group includes two or more IO cell columns, and the two or more IO cell columns are aligned in the second direction such that the lower power supply voltage regions face each other or the higher power supply voltage regions face each other.

公开(公告)号：US20180040521A1

公开(公告)日：2018-02-08

申请号：US15785531

申请日：2017-10-17

申请人： Renesas Electronics Corporation

发明人： Bunji YASUMURA ,  Fumio TSUCHIYA ,  Hisanori ITO ,  Takuji IDE ,  Naoki KAWANABE ,  Masanao SATO

IPC分类号： H01L21/66 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L22/32 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/0613 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/30107 ,  H01L2924/3512 ,  H01L2924/00

摘要： A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.

公开(公告)号：US09768155B2

公开(公告)日：2017-09-19

申请号：US14745203

申请日：2015-06-19

申请人： STATS ChipPAC, Ltd.

发明人： Yaojian Lin ,  Kang Chen ,  Seung Wook Yoon

IPC分类号： H01L25/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/538 ,  H01L23/552 ,  H01L21/683 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00

CPC分类号： H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/03 ,  H01L2224/03002 ,  H01L2224/03003 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0613 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/24137 ,  H01L2224/48091 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81805 ,  H01L2224/82005 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

公开(公告)号：US20170084559A1

公开(公告)日：2017-03-23

申请号：US15230889

申请日：2016-08-08

申请人： Samsung Electronics Co., Ltd.

发明人： Myeong Soon Park ,  Hyunsoo Chung ,  Won-young Kim ,  Ae-nee Jang ,  Chanho Lee

IPC分类号： H01L23/00

CPC分类号： H01L23/50 ,  H01L24/02 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06139 ,  H01L2224/06151 ,  H01L2224/06152 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/06159 ,  H01L2224/0616 ,  H01L2224/06165 ,  H01L2224/06169 ,  H01L2224/06177 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/0613

摘要： Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.

公开(公告)号：US20150318249A1

公开(公告)日：2015-11-05

申请号：US14800955

申请日：2015-07-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hsien-Wei CHEN

IPC分类号： H01L23/00

CPC分类号： H01L24/06 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/0603 ,  H01L2224/0612 ,  H01L2224/0613 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06179 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/2064 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A semiconductor chip includes a first conductive pad, a second conductive pad and a third conductive pad. The semiconductor chip also includes a first under bump metallurgy (UBM) structure, a second UBM structure, and a third UBM structure. The first conductive pad is electrically coupled to a circuit over a substrate, the second conductive pad is over a corner region of the substrate and free from being electrically coupled to the circuit over the substrate. The first conductive pad is closer to a geometric center of the semiconductor chip than the second conductive pad. The third conductive pad is over a region of the substrate between the first conductive pad and the second conductive pad. The third conductive pad has a pad width greater than a pad width of the first conductive pad and less than a pad width of the second conductive pad.

摘要翻译： 半导体芯片包括第一导电焊盘，第二导电焊盘和第三导电焊盘。 该半导体芯片还包括第一下凸块冶金（UBM）结构，第二UBM结构和第三UBM结构。 第一导电焊盘电耦合到衬底上的电路，第二导电焊盘位于衬底的角部区域上，并且不与衬底上的电路电耦合。 第一导电焊盘比第二导电焊盘更靠近半导体芯片的几何中心。 第三导电焊盘在第一导电焊盘和第二导电焊盘之间的衬底的区域之上。 第三导电焊盘的焊盘宽度大于第一导电焊盘的焊盘宽度，并小于第二导电焊盘的焊盘宽度。