公开(公告)号：US09847324B2

公开(公告)日：2017-12-19

申请号：US14730030

申请日：2015-06-03

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L25/00 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L25/10 ,  H01L25/07 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/04 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/03002 ,  H01L2224/03003 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/0613 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14104 ,  H01L2224/16111 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/24137 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/82005 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2224/11 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/13015 ,  H01L2224/81

Abstract: A semiconductor device has a temporary carrier. A semiconductor die is oriented with an active surface toward, and mounted to, the temporary carrier. An encapsulant is deposited with a first surface over the temporary carrier and a second surface, opposite the first surface, is deposited over a backside of the semiconductor die. The temporary carrier is removed. A portion of the encapsulant in a periphery of the semiconductor die is removed to form an opening in the first surface of the encapsulant. An interconnect structure is formed over the active surface of the semiconductor die and extends into the opening in the encapsulant layer. A via is formed and extends from the second surface of the encapsulant to the opening. A first bump is formed in the via and electrically connects to the interconnect structure.

公开(公告)号：US20160233203A1

公开(公告)日：2016-08-11

申请号：US15131821

申请日：2016-04-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen

IPC: H01L25/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L25/065 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/03003 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/0905 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13008 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13311 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2518 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/92 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2221/68304 ,  H01L21/304 ,  H01L2221/68381 ,  H01L2224/03 ,  H01L2924/01074 ,  H01L2224/05655 ,  H01L2924/00011 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

公开(公告)号：US09287227B2

公开(公告)日：2016-03-15

申请号：US14547459

申请日：2014-11-19

Applicant: STMICROELECTRONICS (SHENZHEN) R&D CO., LTD.

Inventor： Jing-En Luan

IPC: H01L23/495 ,  H01L21/00 ,  H01R9/00 ,  H01L23/00 ,  H01L23/48 ,  H01L23/433 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49531 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76885 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/481 ,  H01L23/482 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/16 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/03003 ,  H01L2224/03334 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06177 ,  H01L2224/09151 ,  H01L2224/12105 ,  H01L2224/16238 ,  H01L2224/32221 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/85 ,  H01L2224/92127 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2224/81 ,  H01L2924/00012

Abstract: An electronic device may include leads, an IC having first and second bond pads, and an encapsulation material adjacent the leads and the IC so the leads extend to a bottom surface of the encapsulation material defining first contact pads. The electronic device may include bond wires between the first bond pads and corresponding ones of the leads, and conductors extending from corresponding ones of the second bond pads to the bottom surface of the encapsulation material defining second contact pads.

Abstract translation: 电子设备可以包括引线，具有第一和第二接合焊盘的IC以及与引线和IC相邻的封装材料，使得引线延伸到限定第一接触焊盘的封装材料的底表面。 电子器件可以包括在第一接合焊盘和相应的引线之间的接合线，以及从第二接合焊盘中的相应焊盘延伸到限定第二接触焊盘的封装材料的底表面的导体。

公开(公告)号：US20150287708A1

公开(公告)日：2015-10-08

申请号：US14745203

申请日：2015-06-19

Applicant: STATS ChipPAC, LTD.

Inventor： Yaojian Lin ,  Kang Chen ,  Seung Wook Yoon

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/03 ,  H01L2224/03002 ,  H01L2224/03003 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0613 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/24137 ,  H01L2224/48091 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81805 ,  H01L2224/82005 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

Abstract translation: 半导体器件具有沉积在半导体管芯的第一表面上并且围绕半导体管芯的密封剂。 在半导体管芯的与第一表面相对的第二表面上形成第一绝缘层。 导电层形成在第一绝缘层上。 通过半导体管芯的覆盖区外的密封剂形成互连结构，并电连接到导电层。 第一绝缘层包括光学透明或半透明材料。 半导体管芯包括被配置为接收穿过第一绝缘层的外部刺激的传感器。 在半导体管芯的第一表面上形成第二绝缘层。 通过半导体管芯的覆盖区外的第一绝缘层形成导电通孔。 多个层叠的半导体器件通过互连结构电连接。

公开(公告)号：US20150270232A1

公开(公告)日：2015-09-24

申请号：US14222475

申请日：2014-03-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L25/065 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/03003 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/0905 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13008 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13311 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2518 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/92 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2221/68304 ,  H01L21/304 ,  H01L2221/68381 ,  H01L2224/03 ,  H01L2924/01074 ,  H01L2224/05655 ,  H01L2924/00011 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

Abstract translation: 本公开的实施例包括半导体封装及其形成方法。 一个实施例是一种半导体封装，其包括包括一个或多个管芯的第一封装，以及在第一封装的第一侧处与第一组接合接头耦合到一个或多个管芯的再分配层。 再分配层包括设置在多于一个钝化层中的多于一个金属层，第一组接合接头直接耦合到一个或多个金属层中的至少一个，以及耦合到第一组连接器 再分配层，第二侧与第一侧相对。

公开(公告)号：US08895368B2

公开(公告)日：2014-11-25

申请号：US14133593

申请日：2013-12-18

Applicant: ChipMOS Technologies Inc.

Inventor： Chien-Hao Wang

IPC: H01L21/44 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L21/568 ,  H01L24/03 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/03003 ,  H01L2224/03334 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2224/13 ,  H01L2924/014

Abstract: A method for manufacturing a chip package structure includes following steps. A carrier having a metal layer is provided. A patterned photoresist layer is formed on the metal layer. The patterned photoresist layer has a plurality of first openings exposing a portion of the metal layer. Connection terminals are formed in the first openings, respectively, and the connection terminals are connected to the metal layer. A chip is placed on the carrier, and first pads of the chip are respectively connected to the connection terminals through a plurality of connection conductors. After the chip is placed on the carrier, the patterned photoresist layer is removed. A encapsulant is formed on the carrier. The encapsulant encapsulates the chip, the connection conductors, and the metal layer. The carrier and the metal layer are removed to expose the connection terminals.

Abstract translation: 制造芯片封装结构的方法包括以下步骤。 提供具有金属层的载体。 在金属层上形成图案化的光致抗蚀剂层。 图案化的光致抗蚀剂层具有暴露金属层的一部分的多个第一开口。 连接端子分别形成在第一开口中，并且连接端子连接到金属层。 将芯片放置在载体上，并且芯片的第一焊盘通过多个连接导体分别连接到连接端子。 将芯片放置在载体上之后，去除图案化的光致抗蚀剂层。 在载体上形成密封剂。 密封剂封装芯片，连接导体和金属层。 移除载体和金属层以露出连接端子。

公开(公告)号：US20140322869A1

公开(公告)日：2014-10-30

申请号：US14133593

申请日：2013-12-18

Applicant: ChipMOS Technologies Inc.

Inventor： Chien-Hao Wang

IPC: H01L21/56 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L21/568 ,  H01L24/03 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/03003 ,  H01L2224/03334 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2224/13 ,  H01L2924/014

Abstract: A method for manufacturing a chip package structure includes following steps. A carrier having a metal layer is provided. A patterned photoresist layer is formed on the metal layer. The patterned photoresist layer has a plurality of first openings exposing a portion of the metal layer. Connection terminals are formed in the first openings, respectively, and the connection terminals are connected to the metal layer. A chip is placed on the carrier, and first pads of the chip are respectively connected to the connection terminals through a plurality of connection conductors. After the chip is placed on the carrier, the patterned photoresist layer is removed. A encapsulant is formed on the carrier. The encapsulant encapsulates the chip, the connection conductors, and the metal layer. The carrier and the metal layer are removed to expose the connection terminals.

Abstract translation: 制造芯片封装结构的方法包括以下步骤。 提供具有金属层的载体。 在金属层上形成图案化的光致抗蚀剂层。 图案化的光致抗蚀剂层具有暴露金属层的一部分的多个第一开口。 连接端子分别形成在第一开口中，并且连接端子连接到金属层。 将芯片放置在载体上，并且芯片的第一焊盘通过多个连接导体分别连接到连接端子。 将芯片放置在载体上之后，去除图案化的光致抗蚀剂层。 在载体上形成密封剂。 密封剂封装芯片，连接导体和金属层。 移除载体和金属层以露出连接端子。

公开(公告)号：US20140262003A1

公开(公告)日：2014-09-18

申请号：US14354134

申请日：2012-11-08

Applicant: Tanaka Kikinzoku Kogyo K.K.

Inventor： Toshinori Ogashiwa ,  Masaaki Kurita ,  Takashi Nishimori ,  Yukio Kanehira

IPC: H01L21/48 ,  H01L21/71

CPC classification number: H01L21/4814 ,  B22F7/08 ,  B23K35/007 ,  B23K35/0244 ,  B23K35/025 ,  B23K35/3006 ,  B23K35/3013 ,  B23K35/322 ,  B23K2035/008 ,  B23K2101/40 ,  B32B15/018 ,  C22C5/02 ,  C22C5/04 ,  C23C18/165 ,  C25D7/00 ,  H01L21/71 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/03003 ,  H01L2224/031 ,  H01L2224/0312 ,  H01L2224/03334 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05671 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/1112 ,  H01L2224/11334 ,  H01L2224/11505 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/1317 ,  H01L2224/13171 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13178 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/94 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/181 ,  Y10T428/12056 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01046 ,  H01L2924/00012

Abstract: A transfer substrate for transferring a metal wiring material to a transfer target including a substrate, at least one metal wiring material formed on the substrate, at least one coating layer formed on a surface of the metal wiring material, and an underlying metal film formed between the substrate and the metal wiring material, in which the metal wiring material is a compact formed by sintering metal powder such as gold powder having a purity of 99.9 wt % or more and an average particle size of 0.01 μm to 1.0 μm, and the coating layer is a predetermined metal such as gold or an alloy having a different composition from that of the metal wiring material and has a total thickness of 1 μm or less, and the metal underlying film is made of a predetermined metal such as gold or an alloy. The transfer substrate can lower heating temperature on the transfer target side.

Abstract translation: 一种用于将金属布线材料转印到包括基底的转印靶上的转印衬底，形成在基底上的至少一种金属布线材料，形成在金属布线材料的表面上的至少一层涂层， 基板和金属布线材料，其中金属布线材料是通过烧结纯度为99.9重量％以上和平均粒径为0.01μm至1.0μm的金粉末等金属粉末形成的压块，以及涂层 层是具有与金属布线材料的组成不同的金或合金的预定金属，其总厚度为1μm以下，金属底膜由金或合金等规定金属构成 。 转印基板可以降低转印目标侧的加热温度。

公开(公告)号：US20140145343A1

公开(公告)日：2014-05-29

申请号：US13841957

申请日：2013-03-15

Applicant: SK HYNIX INC.

Inventor： Jong Hoon KIM ,  Pil Soon BAE

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02379 ,  H01L2224/03003 ,  H01L2224/0311 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/03334 ,  H01L2224/03462 ,  H01L2224/0348 ,  H01L2224/03505 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0579 ,  H01L2224/05839 ,  H01L2224/05847 ,  H01L2224/11464 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A semiconductor device comprises: a semiconductor structure formed with openings for exposing pads on an one surface thereof, a first conductive layer formed in the openings to make the one surface of the semiconductor structure more uniform, and conductive patterns formed on portions of the one surface of the semiconductor structure including the first conductive layers.

Abstract translation: 半导体器件包括：形成有用于在其一个表面上暴露焊盘的开口的半导体结构，形成在所述开口中的第一导电层，以使所述半导体结构的所述一个表面更均匀;以及形成在所述一个表面的部分上的导电图案 包括第一导电层的半导体结构。

公开(公告)号：US20130168870A1

公开(公告)日：2013-07-04

申请号：US13340770

申请日：2011-12-30

Applicant: Edward Fuergut ,  Joachim Mahler

Inventor： Edward Fuergut ,  Joachim Mahler

IPC: H01L21/56 ,  H01L23/522

CPC classification number: H01L23/49517 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/03003 ,  H01L2224/03438 ,  H01L2224/0344 ,  H01L2224/03602 ,  H01L2224/0361 ,  H01L2224/04105 ,  H01L2224/05026 ,  H01L2224/051 ,  H01L2224/05571 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A method for manufacturing an electronic interconnect device is described, the method comprising: providing an electronic members each having one or more electrical contacts on a first member side thereof; providing a carrier having a carrier base and having sets of one or more electrically conductive projections on a surface of the carrier base; attaching the electronic members with the corresponding contacts thereof to the respective set of projections to thereby electrically connect the one or more electrical contacts of the respective chip with the corresponding one or more electrically conductive projections of the respective set; encapsulating exposed portions of the electronic member with an encapsulating material to form an encapsulation.

Abstract translation: 描述了一种用于制造电子互连器件的方法，所述方法包括：在其第一部件侧上提供每个具有一个或多个电触点的电子部件; 提供具有载体基底并且在载体基底的表面上具有一组或多个导电突起的载体; 将具有其相应触点的电子部件附接到相应的一组突起，从而将相应芯片的一个或多个电触点与相应组的相应的一个或多个导电突起电连接; 用封装材料封装电子部件的暴露部分以形成封装。