公开(公告)号：US20140145343A1

公开(公告)日：2014-05-29

申请号：US13841957

申请日：2013-03-15

Applicant: SK HYNIX INC.

Inventor： Jong Hoon KIM ,  Pil Soon BAE

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02379 ,  H01L2224/03003 ,  H01L2224/0311 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/03334 ,  H01L2224/03462 ,  H01L2224/0348 ,  H01L2224/03505 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0579 ,  H01L2224/05839 ,  H01L2224/05847 ,  H01L2224/11464 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A semiconductor device comprises: a semiconductor structure formed with openings for exposing pads on an one surface thereof, a first conductive layer formed in the openings to make the one surface of the semiconductor structure more uniform, and conductive patterns formed on portions of the one surface of the semiconductor structure including the first conductive layers.

Abstract translation: 半导体器件包括：形成有用于在其一个表面上暴露焊盘的开口的半导体结构，形成在所述开口中的第一导电层，以使所述半导体结构的所述一个表面更均匀;以及形成在所述一个表面的部分上的导电图案 包括第一导电层的半导体结构。

公开(公告)号：US20190333910A1

公开(公告)日：2019-10-31

申请号：US16186344

申请日：2018-11-09

Applicant: SK hynix Inc.

Inventor： Chanho SHIN ,  Seunghwan KIM ,  Pil Soon BAE ,  Hwijo JEONG

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00

Abstract: A method of stacking semiconductor dies includes attaching a lower semiconductor die to a base substrate with an adhesive layer and attaching an upper semiconductor die to the lower semiconductor die with another adhesive layer. A thermo-compression bonding technique is applied to the upper semiconductor die to cure the adhesive layers and to bond the upper semiconductor die to the lower semiconductor die.

公开(公告)号：US20170170127A1

公开(公告)日：2017-06-15

申请号：US15243296

申请日：2016-08-22

Applicant: SK hynix Inc.

Inventor： Hyeong Seok CHOI ,  Ki Jun SUNG ,  Jong Hoon KIM ,  Young Geun YOO ,  Pil Soon BAE

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/552 ,  H01L23/562 ,  H01L24/14 ,  H01L24/19 ,  H01L24/97 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83132 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/83

Abstract: According to various embodiments, there may be provided packages, semiconductors, and wafer level packages, and there may be provided methods of manufacturing packages, semiconductors, and wafer level packages. A method of manufacturing a wafer level package may include forming alignment marks at a surface of a protection wafer, mounting semiconductor dice on the protection wafer using the alignment marks, forming a first dielectric layer covering the semiconductor dice, planarizing a top surface of the first photosensitive layer, exposuring and developing portions of the planarized first dielectric layer to form opening portions exposing portions of the semiconductor dice, and forming redistribution lines on the first photosensitive dielectric layer. A second dielectric layer may be formed to cover the redistribution lines. Related wafer level packages may also be provided.

公开(公告)号：US20160225744A1

公开(公告)日：2016-08-04

申请号：US14748037

申请日：2015-06-23

Applicant: SK Hynix Inc.

Inventor： Jong Hyun NAM ,  Pil Soon BAE

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48471 ,  H01L2224/85423 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

Abstract: A semiconductor package includes a package substrate having a cavity therein and a second internal contact portion, a semiconductor die disposed in the cavity of the package substrate and having a first internal contact portion, a bonding wire connecting the first internal contact portion to the second internal contact portion, and an encapsulation part covering surfaces of the semiconductor die and the package substrate and providing an opening that exposes a first external contact portion of the bonding wire. Related memory cards and related electronic systems are also provided.

Abstract translation: 半导体封装包括其中具有空腔的封装衬底和第二内部接触部分，设置在封装衬底的空腔中的半导体管芯，并具有第一内部接触部分，将第一内部接触部分连接到第二内部接合部分的接合线 接触部分，以及覆盖半导体管芯和封装基板的表面的封装部分，并提供暴露接合线的第一外部接触部分的开口。 还提供了相关的存储卡和相关的电子系统。