公开(公告)号：US06407459B2

公开(公告)日：2002-06-18

申请号：US09853950

申请日：2001-05-10

Applicant: Yong Hwan Kwon ,  Sa Yoon Kang

Inventor： Yong Hwan Kwon ,  Sa Yoon Kang

IPC: H01L2144

CPC classification number: H01L24/94 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/03003 ,  H01L2224/03438 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2224/02 ,  H01L2924/00 ,  H01L2224/03

Abstract: A semiconductor package which includes: a semiconductor integrated circuit having chip pads formed thereon; interconnection bumps overlying on the chip pads; a patterned metal layer connecting to the interconnection bumps; a first dielectric layer under the patterned metal layer; a second dielectric layer overlying on the patterned metal layer; and terminal pads connecting to the patterned metal layer. The semiconductor package can further include external terminals connecting to the terminal pads, a third dielectric layer filling a gap between the first dielectric layer and the semiconductor integrated circuit.

Abstract translation: 一种半导体封装件，包括：其上形成有芯片焊盘的半导体集成电路; 互连凸块覆盖在芯片焊盘上; 连接到互连凸块的图案化金属层; 图案化金属层下面的第一介电层; 覆盖在图案化金属层上的第二电介质层; 以及连接到图案化金属层的端子焊盘。 半导体封装还可以包括连接到端子焊盘的外部端子，填充第一介电层和半导体集成电路之间的间隙的第三介电层。

公开(公告)号：US20010020737A1

公开(公告)日：2001-09-13

申请号：US09853950

申请日：2001-05-10

Inventor： Yong Hwan Kwon ,  Sa Yoon Kang

IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50 ,  H01L023/02 ,  H01L023/48 ,  H01L023/52

CPC classification number: H01L24/94 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/03003 ,  H01L2224/03438 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2224/02 ,  H01L2924/00 ,  H01L2224/03

Abstract: A method for manufacturing a chip scale package includes: providing a redistribution substrate; attaching a semiconductor wafer to the redistribution substrate; forming external terminals on the redistribution substrate; and separating the semiconductor wafer and the redistribution substrate into individual integrated circuits. The method can further include forming a buffer layer by filling a gap between the semiconductor wafer and the redistribution substrate with a dielectric material. Another method is the same as the method described above except that instead of the semiconductor wafer, individual integrated circuit chips attach to the redistribution substrate. Meanwhile, a semiconductor package includes: a semiconductor integrated circuit having chip pads formed thereon; interconnection bumps overlying on the chip pads; a patterned metal layer connecting to the interconnection bumps; a first dielectric layer under the patterned metal layer; a second dielectric layer overlying on the patterned metal layer; and terminal pads connecting to the patterned metal layer. The semiconductor package can further include external terminals connecting to the terminal pads, a third dielectric layer filling a gap between the first dielectric layer and the semiconductor integrated circuit.

Abstract translation: 芯片级封装的制造方法包括：提供再分布基板; 将半导体晶片附接到再分布基板; 在再分布基板上形成外部端子; 以及将半导体晶片和再分配基板分离成单独的集成电路。 该方法还可以包括通过用介电材料填充半导体晶片和再分布基板之间的间隙来形成缓冲层。 另一方法与上述方法相同，除了代替半导体晶片，各个集成电路芯片附着到再分布基板。 同时，半导体封装包括：其上形成有芯片焊盘的半导体集成电路; 互连凸块覆盖在芯片焊盘上; 连接到互连凸块的图案化金属层; 图案化金属层下面的第一介电层; 覆盖在图案化金属层上的第二电介质层; 以及连接到图案化金属层的端子焊盘。 半导体封装还可以包括连接到端子焊盘的外部端子，填充第一介电层和半导体集成电路之间的间隙的第三介电层。

公开(公告)号：US09490193B2

公开(公告)日：2016-11-08

申请号：US13309163

申请日：2011-12-01

Applicant: Alexander Heinrich ,  Michael Juerss ,  Konrad Roesl ,  Oliver Eichinger ,  Kok Chai Goh ,  Tobias Schmidt

Inventor： Alexander Heinrich ,  Michael Juerss ,  Konrad Roesl ,  Oliver Eichinger ,  Kok Chai Goh ,  Tobias Schmidt

IPC: H01L29/43 ,  H01L29/45 ,  H01L23/482 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L24/32 ,  H01L23/4827 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L29/43 ,  H01L29/45 ,  H01L2224/03438 ,  H01L2224/0345 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/08503 ,  H01L2224/2745 ,  H01L2224/29082 ,  H01L2224/29084 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29118 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29184 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/83191 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83464 ,  H01L2224/83469 ,  H01L2224/83815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01048 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01023 ,  H01L2924/01015 ,  H01L2924/00

Abstract: The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Abstract translation: 电子设备包括载体，附着到载体的半导体衬底以及设置在半导体衬底和载体之间的层系统。 层系统包括设置在半导体衬底上的电接触层。 功能层设置在电接触层上。 粘附层设置在功能层上。 在粘合层和载体之间设置焊料层。

公开(公告)号：US20140273347A1

公开(公告)日：2014-09-18

申请号：US13903700

申请日：2013-05-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pin-Nan Tseng ,  Chia-Shiung Tsai ,  Ping-Yin Liu

IPC: H01L23/00 ,  H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/76838 ,  H01L24/03 ,  H01L2224/03003 ,  H01L2224/03438 ,  H01L2924/13091 ,  H01L2924/00

Abstract: Methods for forming an integrated device using CMOS processing with wafer bonding. In an embodiment, a method is disclosed that includes defining an integrated circuit function using a front-end substrate having one or more active devices and a back-end substrate having connections formed in metal layers in dielectric material, wherein the back-end substrate is free from active devices; manufacturing the front-end substrate in a first semiconductor process; more or less simultaneously, manufacturing the back-end substrate in a second semiconductor process; physically contacting bonding surfaces of the front-end substrate and the back-end substrate; and performing wafer bonding to form bonds between the front-end and back-end substrates to form an integrated circuit. Additional methods are disclosed.

Abstract translation: 利用晶片接合的CMOS处理形成集成器件的方法。 在一个实施例中，公开了一种方法，其包括使用具有一个或多个有源器件的前端衬底和具有形成在介电材料中的金属层中的连接的后端衬底定义集成电路功能，其中后端衬底是 没有活动设备; 在第一半导体工艺中制造前端衬底; 或多或少同时地在第二半导体工艺中制造后端衬底; 物理接触前端基板和后端基板的接合表面; 并执行晶片接合以在前端和后端衬底之间形成结合，以形成集成电路。 公开了另外的方法。

公开(公告)号：US20190006311A1

公开(公告)日：2019-01-03

申请号：US16126190

申请日：2018-09-10

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Michael Juerss ,  Konrad Roesl ,  Oliver Eichinger ,  Kok Chai Goh ,  Tobias Schmidt

IPC: H01L23/00 ,  H01L29/45 ,  H01L29/43 ,  H01L23/482 ,  H01L23/495

CPC classification number: H01L24/32 ,  H01L23/4827 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L29/43 ,  H01L29/45 ,  H01L2224/03438 ,  H01L2224/0345 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/08503 ,  H01L2224/2745 ,  H01L2224/29082 ,  H01L2224/29084 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29118 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29184 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/83191 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83464 ,  H01L2224/83469 ,  H01L2224/83815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01048 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01015 ,  H01L2924/00

Abstract: A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer.

公开(公告)号：US20170025375A1

公开(公告)日：2017-01-26

申请号：US15282927

申请日：2016-09-30

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Michael Juerss ,  Konrad Roesl ,  Oliver Eichinger ,  Kok Chai Goh ,  Tobias Schmidt

IPC: H01L23/00 ,  H01L23/495

CPC classification number: H01L24/32 ,  H01L23/4827 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L29/43 ,  H01L29/45 ,  H01L2224/03438 ,  H01L2224/0345 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/08503 ,  H01L2224/2745 ,  H01L2224/29082 ,  H01L2224/29084 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29118 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29184 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/83191 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83464 ,  H01L2224/83469 ,  H01L2224/83815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01048 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01015 ,  H01L2924/00

Abstract: An electric device with a multi-layer contact is disclosed. In an embodiment, the electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Abstract translation: 公开了具有多层接触的电气设备。 在一个实施例中，电子设备包括载体，连接到载体的半导体衬底以及设置在半导体衬底和载体之间的层系统。 层系统包括设置在半导体衬底上的电接触层。 功能层设置在电接触层上。 粘附层设置在功能层上。 在粘合层和载体之间设置焊料层。

公开(公告)号：US20060091524A1

公开(公告)日：2006-05-04

申请号：US11262758

申请日：2005-11-01

Applicant: Seiji Karashima ,  Yoshihisa Yamashita ,  Seiichi Nakatani ,  Toshiyuki Kojima ,  Shingo Komatsu ,  Satoru Tomekawa

Inventor： Seiji Karashima ,  Yoshihisa Yamashita ,  Seiichi Nakatani ,  Toshiyuki Kojima ,  Shingo Komatsu ,  Satoru Tomekawa

IPC: H01L23/12

CPC classification number: H01L21/486 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/03438 ,  H01L2224/0344 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05169 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/16 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/82047 ,  H01L2224/92144 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor module, comprising: a semiconductor element having a principal face on which an element electrode is formed; and a film member comprising an insulating resin layer having a front face and a rear face which is opposite to said front face, and a wiring pattern formed on the rear face of said layer, wherein said semiconductor element is superposed on said film member so that the principal face of said semiconductor element is in contact with the front face of the insulating resin layer of said film member; and a part of the wiring pattern of said film member extends through said insulating resin layer, so that said part is in contact with the element electrode of said semiconductor element.

Abstract translation: 一种半导体模块，包括：具有形成元件电极的主面的半导体元件; 以及膜构件，其包括具有与所述正面相对的正面和背面的绝缘树脂层和形成在所述层的背面上的布线图案，其中所述半导体元件叠置在所述膜构件上，使得 所述半导体元件的主面与所述膜构件的绝缘树脂层的前表面接触; 并且所述膜部件的布线图形的一部分延伸穿过所述绝缘树脂层，使得所述部分与所述半导体元件的元件电极接触。

公开(公告)号：US20240088087A1

公开(公告)日：2024-03-14

申请号：US18509357

申请日：2023-11-15

Applicant: Infineon Technologies AG

Inventor： Alexander HEINRICH ,  Michael JUERSS ,  Konrad ROESL ,  Oliver EICHINGER ,  Kok Chai GOH ,  Tobias SCHMIDT

IPC: H01L23/00 ,  H01L23/482 ,  H01L23/495 ,  H01L29/43 ,  H01L29/45

CPC classification number: H01L24/32 ,  H01L23/4827 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L29/43 ,  H01L29/45 ,  H01L2224/03438 ,  H01L2224/0345 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/08503 ,  H01L2224/2745 ,  H01L2224/29082 ,  H01L2224/29084 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29118 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29184 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/83191 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83464 ,  H01L2224/83469 ,  H01L2224/83815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01048 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/1776

Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.

公开(公告)号：US11842975B2

公开(公告)日：2023-12-12

申请号：US16679883

申请日：2019-11-11

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Michael Juerss ,  Konrad Roesl ,  Oliver Eichinger ,  Kok Chai Goh ,  Tobias Schmidt

IPC: H01L29/43 ,  H01L23/00 ,  H01L29/45 ,  H01L23/495 ,  H01L23/482

CPC classification number: H01L24/32 ,  H01L23/4827 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L29/43 ,  H01L29/45 ,  H01L2224/0345 ,  H01L2224/03438 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/08503 ,  H01L2224/2745 ,  H01L2224/291 ,  H01L2224/29082 ,  H01L2224/29084 ,  H01L2224/29101 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29118 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29184 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/8346 ,  H01L2224/83191 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/83469 ,  H01L2224/83815 ,  H01L2924/014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01048 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/1776 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2224/291 ,  H01L2924/014 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05139 ,  H01L2924/00014 ,  H01L2224/05171 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/01074 ,  H01L2224/05184 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2924/00014 ,  H01L2224/05669 ,  H01L2924/00014 ,  H01L2224/29111 ,  H01L2924/00014 ,  H01L2224/29118 ,  H01L2924/00014 ,  H01L2224/29109 ,  H01L2924/00014 ,  H01L2224/29105 ,  H01L2924/00014 ,  H01L2224/29113 ,  H01L2924/00014 ,  H01L2224/291 ,  H01L2924/01048 ,  H01L2224/83447 ,  H01L2924/00014 ,  H01L2224/8346 ,  H01L2924/00014 ,  H01L2224/83444 ,  H01L2924/00014 ,  H01L2224/83439 ,  H01L2924/00014 ,  H01L2224/83464 ,  H01L2924/00014 ,  H01L2224/83469 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/01023 ,  H01L2224/05655 ,  H01L2924/01015 ,  H01L2224/83455 ,  H01L2924/01023 ,  H01L2224/83455 ,  H01L2924/01015 ,  H01L2224/29139 ,  H01L2924/00014 ,  H01L2224/29144 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/00 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/1305 ,  H01L2924/00

Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.

公开(公告)号：US20150270247A1

公开(公告)日：2015-09-24

申请号：US14447426

申请日：2014-07-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Der-Chyang Yeh ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/02319 ,  H01L2224/03438 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/11332 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/96 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/13124 ,  H01L2924/01082 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/2064 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/01074

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

Abstract translation: 本公开的实施例包括半导体封装及其形成方法。 一个实施例是一种半导体封装，其包括包括一个或多个管芯的第一封装，以及在第一封装的第一侧处与第一组接合接头耦合到一个或多个管芯的再分配层。 再分配层包括设置在多于一个钝化层中的多于一个金属层，第一组接合接头直接耦合到一个或多个金属层中的至少一个，以及耦合到第一组连接器 再分配层，第二侧与第一侧相对。