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公开(公告)号：US12119322B2
公开(公告)日：2024-10-15
申请号：US18014272
申请日：2021-06-28
Applicant: SUPERUFO291 TEC
Inventor： Akira Fukui , Toshie Fukui
CPC classification number: H01L24/29 , B23K35/0233 , B23K35/3006 , B23K2101/40 , H01L24/05 , H01L24/32 , H01L2224/05155 , H01L2224/05573 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/2908 , H01L2224/29111 , H01L2224/29124 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/32245 , H01L2924/0132 , H01L2924/10272 , H01L2924/13055
Abstract: A bonding member 10 used for bonding a semiconductor device 20 and a substrate 30, the bonding member including: a thermal stress relieving layer 11 made of any of Ag, Cu, Au, and Al; a first Ag brazing material layer 12 containing Ag and Sn as main components and provided on a side of the thermal stress relieving layer to which the semiconductor device is bonded; a second Ag brazing material layer 13 containing Ag and Sn as main components and provided on a side of the thermal stress relieving layer to which the substrate is bonded; a first barrier layer 14 made of Ni and/or Ni alloy and provided between the thermal stress relieving layer and the first Ag brazing material layer; and a second barrier layer 15 made of Ni and/or Ni alloy and provided between the stress relieving layer and the second Ag brazing material layer, in which a thermal conductivity of the bonding member after a power cycle test is 200 W/m·K or more.
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公开(公告)号：US20240335912A1
公开(公告)日：2024-10-10
申请号：US18750260
申请日：2024-06-21
Applicant: Infineon Technologies AG
Inventor： Alexander Heinrich , Alexander Roth , Catharina Wille
IPC: B23K35/02 , B22F1/052 , B23K35/30 , B23K101/40 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/495
CPC classification number: B23K35/0244 , B22F1/052 , B23K35/0227 , B23K35/3033 , H01L21/56 , H01L23/3121 , H01L23/49582 , H01L24/27 , H01L24/29 , B22F2301/15 , B22F2304/10 , B23K2101/40 , H01L2224/2746 , H01L2224/29111 , H01L2224/29118 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29164 , H01L2224/29169
Abstract: A layer structure includes a first layer including at least one material selected from a first group consisting of nickel, copper, gold, silver, palladium, tin, zinc, platinum, and an alloy of any of these materials; a third layer including at least one material selected from a second group consisting of nickel, copper, gold, palladium, tin, silver, zinc, platinum, and an alloy of any of these materials; and a second layer between the first layer and the third layer. The second layer consists of or essentially consists of nickel and tin. The second layer includes an intermetallic phase of nickel and tin. Methods of forming the layer structure, a chip package and a chip arrangement are also described.
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公开(公告)号：US12080660B2
公开(公告)日：2024-09-03
申请号：US17228978
申请日：2021-04-13
Applicant: CREE, INC.
Inventor： Xikun Zhang , Dejiang Chang , Bill Agar , Michael Lefevre , Alexander Komposch
IPC: H01L23/66 , H01L23/00 , H01L23/495 , H01L23/498 , H01L25/00 , H01L25/07 , H01L29/16
CPC classification number: H01L23/66 , H01L23/49503 , H01L23/49568 , H01L23/49575 , H01L23/49844 , H01L24/27 , H01L24/32 , H01L24/83 , H01L24/95 , H01L25/072 , H01L25/50 , H01L29/16 , H01L23/49534 , H01L23/49537 , H01L23/49582 , H01L23/49586 , H01L24/29 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/92 , H01L2223/6644 , H01L2223/6672 , H01L2224/29101 , H01L2224/29111 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/2919 , H01L2224/32245 , H01L2224/45014 , H01L2224/48091 , H01L2224/48247 , H01L2224/49111 , H01L2224/49175 , H01L2224/73265 , H01L2224/83121 , H01L2224/83136 , H01L2224/83192 , H01L2224/83801 , H01L2224/83815 , H01L2224/8384 , H01L2224/83855 , H01L2224/92247 , H01L2924/00014 , H01L2924/01029 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/1033 , H01L2924/13091 , H01L2924/19041 , H01L2924/00014 , H01L2224/45099 , H01L2224/48091 , H01L2924/00014 , H01L2224/8384 , H01L2924/00014 , H01L2224/83801 , H01L2924/00014 , H01L2224/2919 , H01L2924/0665 , H01L2924/00014 , H01L2224/29101 , H01L2924/014 , H01L2924/00014 , H01L2224/29144 , H01L2924/0105 , H01L2224/29139 , H01L2924/0105 , H01L2224/29147 , H01L2924/0105 , H01L2224/83855 , H01L2924/00014 , H01L2224/73265 , H01L2224/32245 , H01L2224/48247 , H01L2924/00012 , H01L2224/92247 , H01L2224/73265 , H01L2224/32245 , H01L2224/48247 , H01L2924/00012
Abstract: A multi-die package includes a thermally conductive flange, a first semiconductor die made of a first semiconductor material attached to the thermally conductive flange via a first die attach material, a second semiconductor die attached to the same thermally conductive flange as the first semiconductor die via a second die attach material, and leads attached to the thermally conductive flange or to an insulating member secured to the flange. The leads are configured to provide external electrical access to the first and second semiconductor dies. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. Additional multi-die package embodiments are described.
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公开(公告)号：US20240243091A1
公开(公告)日：2024-07-18
申请号：US18415074
申请日：2024-01-17
Applicant: THE INDIUM CORPORATION OF AMERICA
Inventor： Richard McDonough , Milos Lazic , David P. Socha
CPC classification number: H01L24/27 , H01L21/4882 , H01L24/29 , H01L24/32 , H01L24/83 , H01L24/16 , H01L24/73 , H01L2224/16221 , H01L2224/2743 , H01L2224/29083 , H01L2224/29101 , H01L2224/29105 , H01L2224/29109 , H01L2224/29111 , H01L2224/29113 , H01L2224/29116 , H01L2224/29118 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29166 , H01L2224/29171 , H01L2224/2918 , H01L2224/29184 , H01L2224/32245 , H01L2224/32506 , H01L2224/73253 , H01L2224/83801 , H01L2924/01048 , H01L2924/0133
Abstract: Thermal interface materials deposited in solid form, in a layered manner, and their uses in electronics assembly are described. In one implementation, a method includes: forming an assembly including multiple solid metal thermal interface materials (TIMs) between a first device and a second device such that a first surface of the solid metal TIMs is in touching relation with a surface of the first device, and a second surface of the solid metal TIMs opposite the first surface is in touching relation with a surface of the second device, the solid metal TIMs including a first solid metal TIM and a second solid metal TIM; and forming a liquid TIM alloy from the solid metal TIMs by heating the assembly above a first solidus temperature of the first solid metal TIM, the liquid TIM alloy having a second solidus temperature below the first solidus temperature.
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5.发明公开
公开(公告)号：US20240170435A1
公开(公告)日：2024-05-23
申请号：US18419382
申请日：2024-01-22
Applicant: Micron Technology, Inc.
Inventor： Eiichi Nakano , Mark E. Tuttle
IPC: H01L23/00 , H01L25/065
CPC classification number: H01L24/29 , H01L24/27 , H01L24/83 , H01L25/0657 , H01L2224/279 , H01L2224/29076 , H01L2224/29147 , H01L2224/29155 , H01L2224/2919 , H01L2224/83851
Abstract: An anisotropic conductive film (ACF) is formed with an ordered array of discrete regions that include a conductive carbon-based material. The discrete regions, which may be formed at small pitch, are embedded in at least one adhesive dielectric material. The ACF may be used to mechanically and electrically interconnect conductive elements of initially-separate semiconductor dice in semiconductor device assemblies. Methods of forming the ACF include forming a precursor structure with the conductive carbon-based material and then joining the precursor structure to a separately-formed structure that includes adhesive dielectric material to be included in the ACF. Sacrificial materials of the precursor structure may be removed and additional adhesive dielectric material formed to embed the discrete regions with the conductive carbon-based material in the adhesive dielectric material of the ACF.
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公开(公告)号：US20240170434A1
公开(公告)日：2024-05-23
申请号：US18193012
申请日：2023-03-30
Applicant: AG MATERIALS TECHNOLOGY CO., LTD.
Inventor： Chien-Hsun CHUANG
IPC: H01L23/00
CPC classification number: H01L24/29 , H01L24/27 , H01L2224/2745 , H01L2224/29082 , H01L2224/29124 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29164 , H01L2224/29166 , H01L2224/29171
Abstract: A back side metallization thin film structure is provided, which includes a wafer and a metallic nano-twinned thin film on the back side of the wafer. A plurality of integrated circuit devices are formed on the front side of the wafer. The metallic nano-twinned thin film includes silver, copper, gold, palladium, or nickel. The metallic nano-twinned thin film has a transition layer near the wafer and a twin layer away from the wafer. The twin layer accounts for at least 70% of the thickness of the metallic nano-twinned thin film and includes parallel-arranged twin boundaries. The parallel-arranged twin boundaries include more than 50% of (111) crystal orientation. The back side metallization thin film structure is formed by activating the wafer surface by ion beam bombardment, followed by an evaporation deposition process performed on the activated wafer surface with simultaneous ion beam bombardment.
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公开(公告)号：US20240162109A1
公开(公告)日：2024-05-16
申请号：US18152615
申请日：2023-01-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hung-Yi Kuo , Chen-Hua Yu , Kuo-Chung Yee , Yu-Jen Lien , Ke-Han Shen , Wei-Kong Sheng , Chung-Shi Liu , Szu-Wei Lu , Tsung-Fu Tsai , Chung-Ju Lee , Chih-Ming Ke
IPC: H01L23/367 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/373 , H10B80/00
CPC classification number: H01L23/3677 , H01L21/56 , H01L23/3128 , H01L23/3736 , H01L24/16 , H01L24/32 , H01L24/33 , H01L24/73 , H10B80/00 , H01L2224/16225 , H01L2224/29124 , H01L2224/29147 , H01L2224/29155 , H01L2224/29166 , H01L2224/29172 , H01L2224/32245 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253
Abstract: In an embodiment, a package includes an integrated circuit device attached to a substrate; an encapsulant disposed over the substrate and laterally around the integrated circuit device, wherein a top surface of the encapsulant is coplanar with the top surface of the integrated circuit device; and a heat dissipation structure disposed over the integrated circuit device and the encapsulant, wherein the heat dissipation structure includes a spreading layer disposed over the encapsulant and the integrated circuit device, wherein the spreading layer includes a plurality of islands, wherein at least a portion of the islands are arranged as lines extending in a first direction in a plan view; a plurality of pillars disposed over the islands of the spreading layer; and nanostructures disposed over the pillars.
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8.发明公开
公开(公告)号：US20240157483A1
公开(公告)日：2024-05-16
申请号：US18281698
申请日：2022-03-14
Applicant: KYOCERA Corporation
Inventor： Tomonao KIKUCHI , Kouki NONOMURA
CPC classification number: B23K35/025 , B22F1/052 , B22F1/056 , B22F1/102 , B22F9/24 , B23K35/302 , B23K35/365 , H01L24/29 , H01L24/32 , B22F2301/10 , B22F2304/054 , B22F2304/058 , B22F2999/00 , H01L24/48 , H01L24/73 , H01L2224/29147 , H01L2224/32245 , H01L2224/48245 , H01L2224/73265
Abstract: A paste composition including first copper particles, wherein the first copper particles are formed by covering copper particles serving as a base material with at least one type of compound selected from the group consisting of an amine compound (a) and a carboxylic acid amine salt (b), and a total content of the amine compound (a) and the carboxylic acid amine salt (b) detected in the paste composition is less than 1 mass % of an entire amount of the paste composition.
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公开(公告)号：US20240113066A1
公开(公告)日：2024-04-04
申请号：US18264719
申请日：2022-01-28
Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Inventor： Takashi IMAHIGASHI
IPC: H01L23/00 , H01S5/0234 , H01S5/026
CPC classification number: H01L24/73 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/32 , H01S5/0234 , H01S5/0261 , H01L24/11 , H01L24/27 , H01L2224/05073 , H01L2224/05573 , H01L2224/05644 , H01L2224/1145 , H01L2224/11466 , H01L2224/1147 , H01L2224/11848 , H01L2224/13014 , H01L2224/13082 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13169 , H01L2224/14136 , H01L2224/16145 , H01L2224/2745 , H01L2224/27466 , H01L2224/2747 , H01L2224/27848 , H01L2224/29011 , H01L2224/29023 , H01L2224/29035 , H01L2224/29082 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29169 , H01L2224/32145 , H01L2224/73203 , H01L2924/01203 , H01L2924/10253 , H01L2924/10329 , H01L2924/10335 , H01L2924/12042 , H01L2924/1426
Abstract: An electronic device according to the present disclosure includes a semiconductor substrate, a chip, a bump, and a sidewall portion. The bump connects a plurality of connection pads provided on the opposing main surfaces of the semiconductor substrate and the chip. The sidewall portion includes a porous metal layer and that annularly surrounds a region where a plurality of bumps is provided, and connects the semiconductor substrate and the chip. The chip has a thermal expansion coefficient different from that of the semiconductor substrate by 0.1 ppm/° C. or more. The chip is a semiconductor laser, and the semiconductor substrate includes a drive circuit that drives the semiconductor laser.
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公开(公告)号：US11908824B2
公开(公告)日：2024-02-20
申请号：US17567168
申请日：2022-01-03
Applicant: JMJ Korea Co., Ltd.
Inventor： Yun Hwa Choi
IPC: H01L23/00 , H01L25/065 , H01L23/498
CPC classification number: H01L24/48 , H01L23/49822 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/41 , H01L24/45 , H01L24/73 , H01L25/0655 , H01L2224/29111 , H01L2224/29139 , H01L2224/29147 , H01L2224/32225 , H01L2224/3701 , H01L2224/404 , H01L2224/411 , H01L2224/4516 , H01L2224/45147 , H01L2224/48091 , H01L2224/48225 , H01L2224/48491 , H01L2224/73265 , H01L2924/35
Abstract: The present invention relates to a semiconductor package in which a metal bridge, which is bent and has elasticity and a non-vertical structure, may protect a semiconductor chip in such a way that push-stress occurring while molding is relieved by being absorbed or dispersed by being diverted, a method of manufacturing the same, and the metal bridge applied to the semiconductor package.
