公开(公告)号：US08617943B2

公开(公告)日：2013-12-31

申请号：US12746440

申请日：2009-07-22

申请人： Takashi Ichiryu ,  Seiichi Nakatani ,  Koichi Hirano ,  Yoshihisa Yamashita ,  Shingo Komatsu

发明人： Takashi Ichiryu ,  Seiichi Nakatani ,  Koichi Hirano ,  Yoshihisa Yamashita ,  Shingo Komatsu

IPC分类号： H01L21/00

CPC分类号： H01L29/78603 ,  H01L24/19 ,  H01L24/82 ,  H01L27/1218 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78681 ,  H01L29/7869 ,  H01L51/0024 ,  H01L51/003 ,  H01L51/0097 ,  H01L51/0541 ,  H01L51/0545 ,  H01L2221/68377 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82102 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： A method for fabricating a flexible semiconductor device includes: preparing a layered film 80 including a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40 which are sequentially formed; etching the first metal layer 10 to form a gate electrode 12g; compression bonding a resin layer 50 to a surface of the layered film 80 provided with the gate electrode 12g to allow the gate electrode 12g to be embedded in the resin layer 50; and etching the second metal layer 40 to form a source electrode 42s and a drain electrode 42d, wherein the inorganic insulating layer 20 on the gate electrode 12g functions as a gate insulating film 22, and the semiconductor layer 30 between the source electrode 42s and drain electrode 42d on the inorganic insulating layer 20 functions as a channel 32.

摘要翻译： 一种制造柔性半导体器件的方法包括：制备包括依次形成的第一金属层10，无机绝缘层20，半导体层30和第二金属层40的层状膜80; 蚀刻第一金属层10以形成栅电极12g; 将树脂层50压接到设置有栅电极12g的层叠膜80的表面，以使栅电极12g嵌入树脂层50中; 并且蚀刻第二金属层40以形成源电极42s和漏电极42d，其中栅电极12g上的无机绝缘层20用作栅极绝缘膜22，并且源电极42s和漏极之间的半导体层30 无机绝缘层20上的电极42d用作通道32。

公开(公告)号：US20130032797A1

公开(公告)日：2013-02-07

申请号：US13641793

申请日：2011-12-19

申请人： Koichi Hirano ,  Shingo Komatsu ,  Yasuteru Saito ,  Naoki Ike

发明人： Koichi Hirano ,  Shingo Komatsu ,  Yasuteru Saito ,  Naoki Ike

IPC分类号： H01L21/336 ,  H01L29/786

CPC分类号： H01L29/7869 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78693

摘要： The present invention achieves a formation of a metal oxide film of a thin film transistor with a simplified process. The present invention is concerned with a method for manufacturing a field-effect transistor comprising a gate electrode, a source electrode, a drain electrode, a channel layer and a gate insulating layer wherein the channel layer is formed by using a metal salt-containing composition comprising a metal salt, a polyvalent carboxylic acid having a cis-form structure of —C(COOH)═C(COOH)—, an organic solvent and a water wherein a molar ratio of the polyvalent carboxylic acid to the metal salt is in the range of 0.5 to 4.0.

摘要翻译： 本发明通过简化的工艺实现了薄膜晶体管的金属氧化物膜的形成。 本发明涉及一种制造场效应晶体管的方法，该场效应晶体管包括栅电极，源电极，漏电极，沟道层和栅极绝缘层，其中通过使用含金属盐的组合物形成沟道层 包括金属盐，具有-C（COOH）= C（COOH） - 的顺式结构的多元羧酸，有机溶剂和水，其中多价羧酸与金属盐的摩尔比为 范围为0.5至4.0。

公开(公告)号：US20090321124A1

公开(公告)日：2009-12-31

申请号：US12489818

申请日：2009-06-23

申请人： Yutaka KUMANO ,  Hideki IWAKI ,  Tetsuyoshi OGURA ,  Shingo KOMATSU ,  Koichi HIRANO

发明人： Yutaka KUMANO ,  Hideki IWAKI ,  Tetsuyoshi OGURA ,  Shingo KOMATSU ,  Koichi HIRANO

IPC分类号： H01R12/06 ,  H05K3/10

CPC分类号： H05K3/4046 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0204 ,  H05K3/4647 ,  H05K2201/10287 ,  H05K2201/10378 ,  H05K2201/10416 ,  H05K2203/0152 ,  Y10T29/49162 ,  H01L2924/00

摘要： A pair of discretionary points on a principal surface of a block are coupled to each other with a metal wire having a length larger than a distance between the pair of discretionary points, liquid resin is applied to the principal surface so as to cover the metal wire and then cured, so that a resin-cured material is formed, and the upper-surface portion of the resin-cured material is removed together with an intermediate portion of the metal wire, and then the block is removed from the resin-cured material.

摘要翻译： 块的主表面上的一对自由点通过长度大于所述一对自由点之间的距离的金属线彼此连接，液体树脂施加到主表面以覆盖金属线 然后固化，从而形成树脂固化材料，树脂固化材料的上表面部分与金属丝的中间部分一起除去，然后将该块从树脂固化材料上除去 。

公开(公告)号：US07390692B2

公开(公告)日：2008-06-24

申请号：US11497169

申请日：2006-08-01

申请人： Yasuhiro Sugaya ,  Toshiyuki Asahi ,  Shingo Komatsu ,  Yoshiyuki Yamamoto ,  Seiichi Nakatani

发明人： Yasuhiro Sugaya ,  Toshiyuki Asahi ,  Shingo Komatsu ,  Yoshiyuki Yamamoto ,  Seiichi Nakatani

IPC分类号： H01L21/00

CPC分类号： H05K3/328 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/94 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2224/2402 ,  H01L2224/24226 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01039 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K1/0373 ,  H05K3/20 ,  H05K3/326 ,  H05K3/4614 ,  H05K3/4626 ,  H05K2201/091 ,  H05K2201/10674 ,  H01L2224/97 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05144 ,  H01L2924/00014 ,  H01L2224/05147

摘要： A semiconductor device (1) of the present invention includes a semiconductor element (103) including electrode parts (104), and a wiring substrate (108) including an insulation layer (101), electrode-part-connection electrodes (102) provided in the insulation layer (101), and external electrodes (107) that is provided in the insulation layer (101) and that is connected electrically with the electrode-part-connection electrodes (102), in which the electrode parts (104) and the electrode-part-connection electrodes (102) are connected electrically with each other. The insulation layer (101) has an elastic modulus measured according to JIS K6911 of not less than 0.1 GP a and not more than 5 GPa, and the electrodes (104) and the electrode-part-connection electrodes (102) are connected by metal joint.

摘要翻译： 本发明的半导体器件（1）包括包括电极部分（104）的半导体元件（103）和包括绝缘层（101）的布线基板（108），电极部分连接电极（102） 绝缘层（101）和设置在绝缘层（101）中并与电极部分连接电极（102）电连接的外部电极（107），其中电极部分（104）和 电极部分连接电极（102）彼此电连接。 绝缘层（101）具有根据JIS K6911测定的弹性模量为0.1GPa以上且5GPa以下，电极（104）和电极部连接用电极（102）通过金属 联合。

公开(公告)号：US07132756B2

公开(公告)日：2006-11-07

申请号：US10692938

申请日：2003-10-24

申请人： Yasuhiro Sugaya ,  Toshiyuki Asahi ,  Shingo Komatsu ,  Yoshiyuki Yamamoto ,  Seiichi Nakatani

发明人： Yasuhiro Sugaya ,  Toshiyuki Asahi ,  Shingo Komatsu ,  Yoshiyuki Yamamoto ,  Seiichi Nakatani

IPC分类号： H01L23/48

CPC分类号： H05K3/328 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/94 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2224/2402 ,  H01L2224/24226 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01039 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K1/0373 ,  H05K3/20 ,  H05K3/326 ,  H05K3/4614 ,  H05K3/4626 ,  H05K2201/091 ,  H05K2201/10674 ,  H01L2224/97 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05144 ,  H01L2924/00014 ,  H01L2224/05147

摘要： A semiconductor device (1) of the present invention includes a semiconductor element (103) including electrode parts (104), and a wiring substrate (108) including an insulation layer (101), electrode-part-connection electrodes (102) provided in the insulation layer (101), and external electrodes (107) that is provided in the insulation layer (101) and that is connected electrically with the electrode-part-connection electrodes (102), in which the electrode parts (104) and the electrode-part-connection electrodes (102) are connected electrically with each other. The insulation layer (101) has an elastic modulus measured according to JIS K6911 of not less than 0.1 GP a and not more than 5 GPa, and the electrodes (104) and the electrode-part-connection electrodes (102) are connected by metal joint.

公开(公告)号：US20060091524A1

公开(公告)日：2006-05-04

申请号：US11262758

申请日：2005-11-01

申请人： Seiji Karashima ,  Yoshihisa Yamashita ,  Seiichi Nakatani ,  Toshiyuki Kojima ,  Shingo Komatsu ,  Satoru Tomekawa

发明人： Seiji Karashima ,  Yoshihisa Yamashita ,  Seiichi Nakatani ,  Toshiyuki Kojima ,  Shingo Komatsu ,  Satoru Tomekawa

IPC分类号： H01L23/12

CPC分类号： H01L21/486 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/03438 ,  H01L2224/0344 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05169 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/16 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/82047 ,  H01L2224/92144 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor module, comprising: a semiconductor element having a principal face on which an element electrode is formed; and a film member comprising an insulating resin layer having a front face and a rear face which is opposite to said front face, and a wiring pattern formed on the rear face of said layer, wherein said semiconductor element is superposed on said film member so that the principal face of said semiconductor element is in contact with the front face of the insulating resin layer of said film member; and a part of the wiring pattern of said film member extends through said insulating resin layer, so that said part is in contact with the element electrode of said semiconductor element.

摘要翻译： 一种半导体模块，包括：具有形成元件电极的主面的半导体元件; 以及膜构件，其包括具有与所述正面相对的正面和背面的绝缘树脂层和形成在所述层的背面上的布线图案，其中所述半导体元件叠置在所述膜构件上，使得 所述半导体元件的主面与所述膜构件的绝缘树脂层的前表面接触; 并且所述膜部件的布线图形的一部分延伸穿过所述绝缘树脂层，使得所述部分与所述半导体元件的元件电极接触。

公开(公告)号：US06975516B2

公开(公告)日：2005-12-13

申请号：US10272599

申请日：2002-10-15

申请人： Toshiyuki Asahi ,  Yasuhiro Sugaya ,  Shingo Komatsu ,  Yoshiyuki Yamamoto ,  Seiichi Nakatani

发明人： Toshiyuki Asahi ,  Yasuhiro Sugaya ,  Shingo Komatsu ,  Yoshiyuki Yamamoto ,  Seiichi Nakatani

IPC分类号： H01L21/98 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16 ,  H05K1/18 ,  H05K7/06

CPC分类号： H01L25/50 ,  H01L21/6835 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/2402 ,  H01L2224/24226 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/82047 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/186 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/10378 ,  H05K2201/10636 ,  H05K2203/061 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/29075

摘要： A component built-in module includes an insulating layer, wirings integrated with both surfaces of the insulating layer, a via connecting the wirings, and one or more components selected from an electronic component and a semiconductor, which is embedded inside of the insulating layer. In this module, at least one of the wirings is formed on a surface of a wiring board, and the components embedded inside of the insulating layer are mounted on and integrated with the wiring board before embedding. This configuration allows the components such as a semiconductor to undergo a mounting inspection and a property inspection before embedding. As a result, the yields of the module can be improved. In addition, since the components are integrated with the wiring board and embedded, the strength thereof can be enhanced.

公开(公告)号：US06955948B2

公开(公告)日：2005-10-18

申请号：US10271937

申请日：2002-10-15

申请人： Toshiyuki Asahi ,  Yasuhiro Sugaya ,  Shingo Komatsu ,  Seiichi Nakatani

发明人： Toshiyuki Asahi ,  Yasuhiro Sugaya ,  Shingo Komatsu ,  Seiichi Nakatani

IPC分类号： H05K1/14 ,  H01L23/538 ,  H05K1/18 ,  H05K3/46 ,  H01L21/44

CPC分类号： H05K1/187 ,  H01L23/5389 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/181 ,  H01L2924/19105 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/10378 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

摘要： A component built-in module includes an electric insulation layer, first wiring patterns in a plurality of layers that are laminated with the electric insulation layer being interposed therebetween, at least one first inner via electrically connecting the first wiring patterns in different layers with each other, and at least one electronic component that is embedded in the electric insulation layer and is mounted on any one of the first wiring patterns in the plurality of layers, wherein at least one of the first inner vias is present in a range that overlaps a range in which the electronic component is present in a lamination direction in which the first wiring patterns are laminated, and has a height in the lamination direction that is smaller than a height of the electronic component. Since the first inner via has a small height, the via diameter can be decreased. Therefore, it is possible to provide a component built-in module that has high reliability and is suitable for high-density component mounting.

摘要翻译： 组件内置模块包括电绝缘层，层间隔着电绝缘层的多个层中的第一布线图案，至少一个第一内通孔，将第一布线图案彼此不同地电连接 以及至少一个电子部件，其嵌入在所述电绝缘层中并且安装在所述多个层中的所述第一布线图案中的任一个上，其中，所述第一内部通孔中的至少一个存在于与所述多个层重叠的范围内 其中电子部件以层叠方式存在，其中第一布线图案被层叠，并且具有比电子部件的高度小的层叠方向的高度。 由于第一内部通孔具有小的高度，所以通孔直径可以减小。 因此，可以提供具有高可靠性并适用于高密度部件安装的部件内置模块。

公开(公告)号：US06855892B2

公开(公告)日：2005-02-15

申请号：US10246476

申请日：2002-09-19

申请人： Shingo Komatsu ,  Seiichi Nakatani ,  Yasuhiro Sugaya ,  Toshiyuki Asahi ,  Yoshiyuki Yamamoto

发明人： Shingo Komatsu ,  Seiichi Nakatani ,  Yasuhiro Sugaya ,  Toshiyuki Asahi ,  Yoshiyuki Yamamoto

IPC分类号： H05K1/18 ,  H05K3/40 ,  H05K3/46 ,  H01R12/04

CPC分类号： H05K3/4617 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/185 ,  H05K3/4069 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0209 ,  H05K2201/10378 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/249996

摘要： An insulation sheet for use in producing a wiring substrate comprises, as via bole conductors, conductive paste filled in via holes formed through the insulation sheet, and a curing-starting temperature of the conductive paste is lower than a melting-starting temperature of the insulation sheet. A wiring substrate is produced by laminating such insulation sheets, that have conductive paste in via holes, and subjecting this laminate to thermo-compression bonding, wherein deformation of via holes and dislocation of the via holes, because of a molten insulation sheet, does not occur.

摘要翻译： 用于制造布线基板的绝缘片包括作为通孔导体的填充有通过绝缘片形成的通孔的导电糊，并且导电糊的固化开始温度低于绝缘的熔融起始温度 片。 通过在通孔中层叠具有导电性糊剂的绝缘片，并对该层压体进行热压接而制造布线基板，由于熔融绝缘片而导致通孔的变形和通孔的位错不会 发生。

公开(公告)号：US06784530B2

公开(公告)日：2004-08-31

申请号：US10346917

申请日：2003-01-17

申请人： Yasuhiro Sugaya ,  Toshiyuki Asahi ,  Shingo Komatsu ,  Yoshiyuki Yamamoto ,  Seiichi Nakatani ,  Satoru Yuhaku ,  Kazuo Ohtani

发明人： Yasuhiro Sugaya ,  Toshiyuki Asahi ,  Shingo Komatsu ,  Yoshiyuki Yamamoto ,  Seiichi Nakatani ,  Satoru Yuhaku ,  Kazuo Ohtani

IPC分类号： H01L2302

CPC分类号： H05K1/187 ,  H01L21/56 ,  H01L21/563 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/29 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83856 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/15787 ,  H01L2924/1627 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2924/3512 ,  H01L2924/00014

摘要： A circuit component built-in module includes: a first electrical insulating substrate made of a mixture containing an inorganic filler and a thermosetting resin; a plurality of wiring patterns formed at least on a principal surface of the first electrical insulating substrate; a semiconductor chip incorporated in the first electrical insulating substrate and connected electrically with the wiring patterns; and inner vias electrically connecting the plurality of wiring patterns with one another, the inner vias passing through the first electrical insulating substrate. In the circuit component built-in module, the semiconductor chip has a thickness of not less than 30 &mgr;m and not more than 100 &mgr;m, and has a non-wired surface ground, and the circuit component built-in module has a thickness in a range of not less than 80 &mgr;m and not more than 200 &mgr;m. With this configuration, the high-performance and compact-size circuit component built-in module in which circuit components are mounted at a high density is provided so as to be used suitably in various types of electronic information devices.

摘要翻译： 电路部件内置模块包括：由含有无机填料和热固性树脂的混合物制成的第一电绝缘基板; 至少形成在所述第一电绝缘基板的主表面上的多个布线图案; 结合在第一电绝缘基板中并与布线图形电连接的半导体芯片; 以及将所述多个布线图案彼此电连接的内部通孔，所述内部通孔穿过所述第一电绝缘基板。 在电路部件内置模块中，半导体芯片的厚度为30μm以上且100μm以下，具有非接线表面接地，电路部件内置模块的厚度为 范围不小于80μm，不大于200μm。 利用这种配置，提供了以高密度安装电路部件的高性能和紧凑型电路部件内置模块，以便适用于各种类型的电子信息装置。