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公开(公告)号：US11935842B2
公开(公告)日：2024-03-19
申请号：US17401616
申请日：2021-08-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shin-Puu Jeng , Clinton Chao , Szu-Wei Lu
IPC: H01L23/00 , H01L21/02 , H01L21/302 , H01L21/304 , H01L21/306 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/3205 , H01L21/56 , H01L21/78 , H01L23/52 , H01L23/58
CPC classification number: H01L23/562 , H01L21/0214 , H01L21/302 , H01L21/304 , H01L21/30625 , H01L21/314 , H01L21/316 , H01L21/3185 , H01L21/32051 , H01L21/563 , H01L21/565 , H01L21/78 , H01L23/52 , H01L24/05 , H01L24/81 , H01L24/85 , H01L24/96 , H01L21/02123 , H01L21/02274 , H01L21/02282 , H01L23/585 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/16227 , H01L2224/32245 , H01L2224/48091 , H01L2224/48106 , H01L2224/48175 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01327 , H01L2924/09701 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/3511 , H01L2224/48091 , H01L2924/00014 , H01L2224/73265 , H01L2224/32245 , H01L2224/48247 , H01L2224/48465 , H01L2224/48247 , H01L2924/00 , H01L2224/48465 , H01L2224/48091 , H01L2924/00 , H01L2924/10253 , H01L2924/00 , H01L2924/13091 , H01L2924/00 , H01L2924/14 , H01L2924/00 , H01L2924/00014 , H01L2224/45099 , H01L2924/00014 , H01L2224/45015 , H01L2924/207
Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.
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公开(公告)号：US20230369277A1
公开(公告)日：2023-11-16
申请号：US18357644
申请日：2023-07-24
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Michael J. SEDDON , Chee Hiong CHEW
IPC: H01L23/00 , H01L21/78 , H01L23/482 , H01L21/683
CPC classification number: H01L24/32 , H01L24/11 , H01L21/78 , H01L23/482 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L21/6836 , H01L24/83 , H01L24/94 , H01L24/28 , H01L24/30 , H01L24/31 , H01L24/33 , H01L2224/13166 , H01L2224/13155 , H01L2224/13147 , H01L2224/13139 , H01L2224/13111 , H01L2924/01327 , H01L2224/11849 , H01L2224/1308 , H01L2224/8481 , H01L2224/8581 , H01L2224/8681 , H01L21/4825
Abstract: Implementations of a semiconductor package may include a pin coupled to a substrate. The pin may include a titanium sublayer, a nickel sublayer, and one of a silver and tin intermetallic layer or a copper and tin intermetallic layer, the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer having a melting temperature greater than 260 degrees Celsius. The one of the silver and tin intermetallic layer or the copper and tin intermetallic layer may be formed by reflowing a tin layer and one of a silver layer or copper layer with a silver layer of the substrate where the substrate may be directly coupled to the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer. The substrate may include a copper layer that was directly coupled with the silver layer before the reflow.
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公开(公告)号：US20230246006A1
公开(公告)日：2023-08-03
申请号：US18162183
申请日：2023-01-31
Applicant: TDK CORPORATION
Inventor： Ryohei KASAI , Takashi WATANABE , Susumu TANIGUCHI , Tomohisa MITOSE , Yuhei HOTTA
IPC: H01L25/075 , H01L23/00
CPC classification number: H01L25/0753 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/13111 , H01L2224/13144 , H01L2224/16225 , H01L2224/05073 , H01L2224/05144 , H01L2224/05139 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/16503 , H01L2924/01327 , H01L2924/12041
Abstract: A joint structure, in which an electronic component and a wiring substrate are joined to each other, includes: a first layer being provided on one side of the electronic component and the wiring substrate, and being composed of a first metal containing Sn; a second layer being provided on the other side of the electronic component and the wiring substrate, and being composed of a second metal that forms an intermetallic compound with Sn; and a third layer being provided at a joint interface between the first layer and the second layer, and being composed of an intermetallic compound of the first metal and the second metal. An average thickness of the third layer is 0.1 μm or more to 0.5 μm or less.
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公开(公告)号：US10037956B2
公开(公告)日：2018-07-31
申请号：US14596851
申请日：2015-01-14
Applicant: Intel Corporation
Inventor： Madhav Datta , Dave Emory , Subhash M. Joshi , Susanne Menezes , Doowon Suh
IPC: H01L23/488 , H01L23/00 , H01L23/498
CPC classification number: H01L24/11 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05572 , H01L2224/05647 , H01L2224/10126 , H01L2224/11009 , H01L2224/1147 , H01L2224/1148 , H01L2224/11849 , H01L2224/11901 , H01L2224/11912 , H01L2224/13023 , H01L2224/13099 , H01L2224/13111 , H01L2224/13116 , H01L2224/13147 , H01L2224/13166 , H01L2924/0002 , H01L2924/01005 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/0104 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01057 , H01L2924/01058 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2224/05552
Abstract: The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device.
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5.发明申请
公开(公告)号：US20180211928A1
公开(公告)日：2018-07-26
申请号：US15936743
申请日：2018-03-27
Inventor： Chia-Lun Chang , Chung-Shi Liu , Hsiu-Jen Lin , Hsien-Wei Chen , Ming-Da Cheng , Wei-Yu Chen
IPC: H01L23/00 , H01L21/56 , H01L23/538 , H01L23/498 , H01L23/29 , H01L21/683 , H01L25/10 , H01L25/065
CPC classification number: H01L24/05 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/293 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L24/03 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/48 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2221/68359 , H01L2224/02126 , H01L2224/02166 , H01L2224/02175 , H01L2224/03015 , H01L2224/0346 , H01L2224/03828 , H01L2224/0383 , H01L2224/0391 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05017 , H01L2224/05025 , H01L2224/05147 , H01L2224/05557 , H01L2224/05559 , H01L2224/05567 , H01L2224/05647 , H01L2224/10156 , H01L2224/11005 , H01L2224/1132 , H01L2224/11334 , H01L2224/11416 , H01L2224/11424 , H01L2224/1181 , H01L2224/11849 , H01L2224/119 , H01L2224/12105 , H01L2224/13026 , H01L2224/13082 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2224/13147 , H01L2224/215 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00 , H01L2924/00014 , H01L2924/01029 , H01L2924/0105 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/06 , H01L2924/0665 , H01L2924/15311 , H01L2924/18162 , H01L2924/00012 , H01L2924/01051 , H01L2924/01047 , H01L2924/01022 , H01L2924/01028 , H01L2924/01046 , H01L2924/01079
Abstract: Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.
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6.发明申请
公开(公告)号：US20180190620A1
公开(公告)日：2018-07-05
申请号：US15905086
申请日：2018-02-26
Applicant: Micron Technology, Inc.
Inventor： Jaspreet S. Gandhi
IPC: H01L25/065 , H01L23/00 , H01L25/00
CPC classification number: H01L25/0657 , H01L24/02 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/18 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05025 , H01L2224/05548 , H01L2224/05567 , H01L2224/05582 , H01L2224/05664 , H01L2224/06181 , H01L2224/11334 , H01L2224/11462 , H01L2224/11464 , H01L2224/13022 , H01L2224/13024 , H01L2224/13025 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13541 , H01L2224/13564 , H01L2224/13582 , H01L2224/13611 , H01L2224/13655 , H01L2224/13664 , H01L2224/1403 , H01L2224/14181 , H01L2224/16058 , H01L2224/16145 , H01L2224/16146 , H01L2224/16148 , H01L2224/16227 , H01L2224/16503 , H01L2224/17181 , H01L2224/32145 , H01L2224/73204 , H01L2224/81191 , H01L2224/81203 , H01L2224/81801 , H01L2224/8181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01327 , H01L2924/014 , H01L2924/1431 , H01L2924/1434 , H01L2924/1436 , H01L2924/3512 , H01L2924/00 , H01L2924/00014
Abstract: Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.
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公开(公告)号：US20180132394A1
公开(公告)日：2018-05-10
申请号：US15670007
申请日：2017-08-07
Applicant: SET North America, LLC
Inventor： Eric Frank Schulte
CPC classification number: H05K13/046 , B32B38/0008 , B32B2310/14 , B32B2457/00 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/50 , H01L2224/0381 , H01L2224/0401 , H01L2224/05552 , H01L2224/05557 , H01L2224/05568 , H01L2224/05655 , H01L2224/11334 , H01L2224/1181 , H01L2224/11831 , H01L2224/13099 , H01L2224/131 , H01L2224/13105 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/1312 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/16145 , H01L2224/81011 , H01L2224/81013 , H01L2224/81054 , H01L2224/81099 , H01L2224/81191 , H01L2224/81193 , H01L2224/812 , H01L2224/81201 , H01L2224/81365 , H01L2224/81895 , H01L2224/81897 , H01L2225/06513 , H01L2225/06565 , H01L2924/00 , H01L2924/0001 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/1431 , H01L2924/1461
Abstract: Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.
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8.发明授权
公开(公告)号：US09935067B2
公开(公告)日：2018-04-03
申请号：US15431514
申请日：2017-02-13
Inventor： Chia-Lun Chang , Chung-Shi Liu , Hsiu-Jen Lin , Hsien-Wei Chen , Ming-Da Cheng , Wei-Yu Chen
IPC: H01L23/00 , H01L23/538 , H01L23/48 , H01L23/52 , H01L29/40 , H01L23/29 , H01L23/498 , H01L21/56 , H01L21/683 , H01L25/065 , H01L25/10
CPC classification number: H01L24/05 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/293 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L24/03 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/48 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2221/68359 , H01L2224/02126 , H01L2224/02166 , H01L2224/02175 , H01L2224/03015 , H01L2224/0346 , H01L2224/03828 , H01L2224/0383 , H01L2224/0391 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05017 , H01L2224/05025 , H01L2224/05147 , H01L2224/05557 , H01L2224/05559 , H01L2224/05567 , H01L2224/05647 , H01L2224/10156 , H01L2224/11005 , H01L2224/1132 , H01L2224/11334 , H01L2224/11416 , H01L2224/11424 , H01L2224/1181 , H01L2224/11849 , H01L2224/119 , H01L2224/12105 , H01L2224/13026 , H01L2224/13082 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2224/13147 , H01L2224/215 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00 , H01L2924/00014 , H01L2924/01029 , H01L2924/0105 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/06 , H01L2924/0665 , H01L2924/15311 , H01L2924/18162 , H01L2924/00012 , H01L2924/01051 , H01L2924/01047 , H01L2924/01022 , H01L2924/01028 , H01L2924/01046 , H01L2924/01079
Abstract: Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.
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公开(公告)号：US20180047689A1
公开(公告)日：2018-02-15
申请号：US15555434
申请日：2016-04-01
Applicant: Intel Corporation
Inventor： Fay HUA
IPC: H01L23/00
CPC classification number: H01L24/13 , B23K35/00 , H01L23/49816 , H01L23/49866 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/11 , H01L2224/0401 , H01L2224/05005 , H01L2224/05147 , H01L2224/05647 , H01L2224/08503 , H01L2224/11 , H01L2224/11334 , H01L2224/11849 , H01L2224/13023 , H01L2224/13111 , H01L2224/13118 , H01L2224/13139 , H01L2924/01327 , H01L2924/014 , H01L2924/206 , H01L2924/3512 , H01L2924/3651 , H01L2924/0103 , H01L2924/01029 , H01L2924/01047 , H01L2924/01079 , H01L2924/01013
Abstract: Embodiments of the invention include a semiconductor device and methods of forming the semiconductor device. In an embodiment the semiconductor device comprises a semiconductor die with one or more die contacts. Embodiments include a reflown solder bump on one or more of the die contacts. In an embodiment, an intermetallic compound (IMC) barrier layer is formed at the interface between the solder bump and the die contact. In an embodiment, the IMC barrier layer is a CuZn IMC and/or a Cu5Zn8 IMC.
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10.发明申请
公开(公告)号：US20180040592A1
公开(公告)日：2018-02-08
申请号：US15788094
申请日：2017-10-19
Applicant: Micron Technology, Inc.
Inventor： Jaspreet S. Gandhi , Wayne H. Huang , James M. Derderian
IPC: H01L25/065 , H01L25/075 , H01L23/40 , H01L23/00 , H01L25/04 , H01L23/498 , H01L23/34 , H01L25/00 , H01L23/367 , H01L23/42
CPC classification number: H01L25/0657 , H01L23/00 , H01L23/34 , H01L23/3675 , H01L23/4012 , H01L23/42 , H01L23/49811 , H01L23/49827 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/81 , H01L25/043 , H01L25/065 , H01L25/0756 , H01L25/50 , H01L2224/05599 , H01L2224/11 , H01L2224/13011 , H01L2224/13019 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/16225 , H01L2224/16503 , H01L2224/73253 , H01L2224/81815 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06586 , H01L2225/06589 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01327 , H01L2924/05032 , H01L2924/15311 , H01L2924/181 , H01L2924/00012
Abstract: Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.
