Abstract:
A power module of a square flat pin-free packaging structure for suppressing the power module from being excessively high in local temperature. The power module includes an insulating resin, a driving chip, a plurality of power chips, and a plurality of metal electrode contacts. The driving chip, the power chips, and the metal electrode contacts are electrically connected through a metal lead according to a predetermined circuit. A plurality of metal heat dissipating disks used for heat dissipation of the power chips and a driving chip lead frame are disposed at the bottom of the insulating resin. A plurality of metal power chip lead frames are disposed on the metal heat dissipating disks, the power chips are disposed on the power chip lead frames, and the drain electrodes of the power chips are electrically connected to the metal heat dissipating disks.
Abstract:
A semiconductor device 100 includes a first insulating material 110 attached to a second main surface 106b of a semiconductor chip 106, and a second insulating material 112 attached to side surfaces of the semiconductor chip 106, the first insulating material 110 and an island 102. The semiconductor chip 106 is fixed to the island 102 via the first insulating material 110 and the second insulating material 112. The first insulating material 110 ensures a high dielectric strength between the semiconductor chip 106 and the island 102. Though the second insulating material 112 having a modulus of elasticity greater than that of the first insulating material 110, the semiconductor chip 106 is firmly attached to the island 102.
Abstract:
An integrated circuit (IC) package includes a die pad and an IC die secured on the die pad. The IC die had outer edges aligned with outer edges of the die pad. An encapsulating material body surrounds the die pad and IC die. Leads extend outwardly from the encapsulating material body and are coupled to the IC die. Each lead has an upper surface coplanar with an upper surface of the IC die. The die pad has a lower surface exposed through the encapsulating material body, and has a thickness greater than a thickness of each of the plurality of leads.
Abstract:
A high temperature, non-cavity package for non-axial electronics is designed using a glass ceramic compound with that is capable of being assembled and operating continuously at temperatures greater that 300-400° C. Metal brazes, such as silver, silver colloid or copper, are used to connect the semiconductor die, lead frame and connectors. The components are also thermally matched such that the packages can be assembled and operating continuously at high temperatures and withstand extreme temperature variations without the bonds failing or the package cracking due to a thermal mismatch.
Abstract:
A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312).
Abstract:
The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.
Abstract:
A high temperature, non-cavity package for non-axial electronics is designed using a glass ceramic compound with that is capable of being assembled and operating continuously at temperatures greater that 300-400° C. Metal brazes, such as silver, silver colloid or copper, are used to connect the semiconductor die, lead frame and connectors. The components are also thermally matched such that the packages can be assembled and operating continuously at high temperatures and withstand extreme temperature variations without the bonds failing or the package cracking due to a thermal mismatch.
Abstract:
A semiconductor device 100 includes a first insulating material 110 attached to a second main surface 106b of a semiconductor chip 106, and a second insulating material 112 attached to side surfaces of the semiconductor chip 106, the first insulating material 110 and an island 102. The semiconductor chip 106 is fixed to the island 102 via the first insulating material 110 and the second insulating material 112. The first insulating material 110 ensures a high dielectric strength between the semiconductor chip 106 and the island 102. Though the second insulating material 112 having a modulus of elasticity greater than that of the first insulating material 110, the semiconductor chip 106 is firmly attached to the island 102.
Abstract:
An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.
Abstract:
An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.