Patent search cpc:"H01L2924/1776" Page 1

1.

发明授权
Semiconductor package having etched foil capacitor integrated into leadframe 有权
Title translation: 具有集成到引线框架中的蚀刻箔电容器的半导体封装

公开(公告)号：US09373572B2

公开(公告)日：2016-06-21

申请号：US14879622

申请日：2015-10-09

Applicant: Texas Instruments Incorporated

Inventor： Gregory E. Howard , Bernardo Gallegos , Rajiv Dunne , Darvin R. Edwards , Siva P. Gurrum , Manu J. Prakuzhy , Donald C. Abbott

IPC: H01L23/02 , H01L23/495 , H01L21/78 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/31

CPC classification number: H01L23/49589 , H01L21/4821 , H01L21/561 , H01L21/78 , H01L23/3107 , H01L23/3114 , H01L23/49503 , H01L23/49541 , H01L23/49582 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49109 , H01L2224/49113 , H01L2224/49171 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01047 , H01L2924/0105 , H01L2924/13091 , H01L2924/15724 , H01L2924/15747 , H01L2924/1576 , H01L2924/17724 , H01L2924/17747 , H01L2924/1776 , H01L2924/181 , H01L2924/19041 , H01L2924/00012 , H01L2924/00014 , H01L2924/00

Abstract: A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal.

Abstract translation: 一种封装半导体器件，包括引线框和多个角形电容器。引线框架包括具有表面和侧壁的结构。角形电容器附接到引线框结构的表面部分。角形电容器具有与结构侧壁共面的侧壁。角形电容器包括附着到结构表面的导电材料。导电材料具有被氧化物覆盖并填充有导电聚合物的孔。由电极顶起的角形电容器由第二金属制成。

2.

发明授权
Semiconductor package having etched foil capacitor integrated into leadframe 有权
Title translation: 具有集成到引线框架中的蚀刻箔电容器的半导体封装

公开(公告)号：US09165873B1

公开(公告)日：2015-10-20

申请号：US14494916

申请日：2014-09-24

Applicant: Texas Instruments Incorporated

Inventor： Gregory E. Howard , Bernardo Gallegos , Rajiv Dunne , Darvin R. Edwards , Siva P. Gurrum , Manu J. Prakuzhy , Donald C. Abbott

IPC: H01L23/02 , H01L23/495

CPC classification number: H01L23/49589 , H01L21/4821 , H01L21/561 , H01L21/78 , H01L23/3107 , H01L23/3114 , H01L23/49503 , H01L23/49541 , H01L23/49582 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49109 , H01L2224/49113 , H01L2224/49171 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01047 , H01L2924/0105 , H01L2924/13091 , H01L2924/15724 , H01L2924/15747 , H01L2924/1576 , H01L2924/17724 , H01L2924/17747 , H01L2924/1776 , H01L2924/181 , H01L2924/19041 , H01L2924/00012 , H01L2924/00014 , H01L2924/00

Abstract: A packaged semiconductor device including a leadframe made of a first metal, the leadframe including structures with surfaces and sidewalls; capacitors attached to surface portions of the leadframe structures, the capacitors having sidewalls coplanar with structure sidewalls; the capacitors including a foil of conductive material attached to the structure surface, the conductive material having pores covered by oxide and filled with conductive polymer, the capacitors topped by electrodes made of a second metal.

Abstract translation: 一种封装半导体器件，包括由第一金属制成的引线框架，所述引线框架包括具有表面和侧壁的结构; 电容器附接到引线框架结构的表面部分，电容器具有与结构侧壁共面的侧壁; 所述电容器包括附着到所述结构表面的导电材料箔，所述导电材料具有由氧化物覆盖并填充有导电聚合物的孔，所述电容器由由第二金属制成的电极顶起。

3.

发明授权
Hermetic package for high CTE mismatch 有权

公开(公告)号：US12119281B2

公开(公告)日：2024-10-15

申请号：US17394093

申请日：2021-08-04

Applicant: Qorvo US, Inc.

Inventor： Dylan Murdock

IPC: H01L23/31 , H01L23/04 , H01L23/10 , H01L23/29 , H01L23/00 , H01L23/373

CPC classification number: H01L23/3142 , H01L23/04 , H01L23/10 , H01L23/291 , H01L23/315 , H01L23/3736 , H01L24/48 , H01L24/49 , H01L2224/48225 , H01L2224/49176 , H01L2924/01042 , H01L2924/01074 , H01L2924/0132 , H01L2924/01403 , H01L2924/05432 , H01L2924/15153 , H01L2924/1517 , H01L2924/15747 , H01L2924/15763 , H01L2924/15787 , H01L2924/16747 , H01L2924/1676 , H01L2924/173 , H01L2924/17747 , H01L2924/1776 , H01L2924/3512

Abstract: The present disclosure relates to a hermetic package capable of handling a high coefficient of thermal expansion (CTE) mismatch configuration. The disclosed hermetic package includes a metal base and multiple segments that are discrete from each other. Herein, a gap exists between every two adjacent ceramic wall segments and is sealed with a connecting material. The ceramic wall segments with the connecting material form a ring wall, where the gap between every two adjacent ceramic wall segments is located at a corner of the ring wall. The metal base is either surrounded by the ring wall or underneath the ring wall.

4.

发明授权
Structure and method for stabilizing leads in wire-bonded semiconductor devices 有权

公开(公告)号：US09824959B2

公开(公告)日：2017-11-21

申请号：US15078071

申请日：2016-03-23

Applicant: Texas Instruments Incorporated

Inventor： Dolores Babaran Milo , Mark Gerald Rosario Pinlac , Bobby Johns Lansangan Villacarlos , Jerry Gomez Cayabyab , Juan Carlo Aro Rimando

IPC: H01L23/495 , H01L23/00 , H01L23/31 , H01L21/48 , H01L23/29

CPC classification number: H01L23/49582 , H01L21/4853 , H01L23/293 , H01L23/3121 , H01L23/49541 , H01L24/05 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/92 , H01L2224/04042 , H01L2224/05624 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48106 , H01L2224/48245 , H01L2224/48247 , H01L2224/48463 , H01L2224/48465 , H01L2224/73265 , H01L2224/78301 , H01L2224/85043 , H01L2224/85045 , H01L2224/85065 , H01L2224/85075 , H01L2224/85205 , H01L2224/85444 , H01L2224/85447 , H01L2224/85464 , H01L2224/8582 , H01L2224/92247 , H01L2924/01028 , H01L2924/01046 , H01L2924/01079 , H01L2924/0132 , H01L2924/01403 , H01L2924/17724 , H01L2924/17747 , H01L2924/1776 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/01001 , H01L2924/01007 , H01L2924/01029 , H01L2924/00

Abstract: A semiconductor device having a leadframe including a pad (101) surrounded by elongated leads (110) spaced from the pad by a gap (113) and extending to a frame, the pad and the leads having a first thickness (115) and a first and an opposite and parallel second surface; the leads having a first portion (112) of first thickness near the gap and a second portion (111) of first thickness near the frame, and a zone (114) of reduced second thickness (116) between the first and second portions; the second surface (112a) of the first lead portions is coplanar with the second surface (111a) of the second portions. A semiconductor chip (220) with a terminal is attached the pad. A metallic wire connection (230) from the terminal to an adjacent lead includes a stitch bond (232) attached to the first surface of the lead.

5.

发明授权
Electronic device with multi-layer contact 有权
Title translation: 电子设备多层接触

公开(公告)号：US09490193B2

公开(公告)日：2016-11-08

申请号：US13309163

申请日：2011-12-01

Applicant: Alexander Heinrich , Michael Juerss , Konrad Roesl , Oliver Eichinger , Kok Chai Goh , Tobias Schmidt

Inventor： Alexander Heinrich , Michael Juerss , Konrad Roesl , Oliver Eichinger , Kok Chai Goh , Tobias Schmidt

IPC: H01L29/43 , H01L29/45 , H01L23/482 , H01L23/00 , H01L23/495

CPC classification number: H01L24/32 , H01L23/4827 , H01L23/49513 , H01L23/49541 , H01L23/49582 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/29 , H01L24/83 , H01L29/43 , H01L29/45 , H01L2224/03438 , H01L2224/0345 , H01L2224/04026 , H01L2224/05083 , H01L2224/05124 , H01L2224/05139 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05669 , H01L2224/08503 , H01L2224/2745 , H01L2224/29082 , H01L2224/29084 , H01L2224/291 , H01L2224/29101 , H01L2224/29105 , H01L2224/29109 , H01L2224/29111 , H01L2224/29113 , H01L2224/29118 , H01L2224/29124 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29166 , H01L2224/29169 , H01L2224/29171 , H01L2224/29184 , H01L2224/32225 , H01L2224/32245 , H01L2224/32503 , H01L2224/32507 , H01L2224/83191 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/8346 , H01L2224/83464 , H01L2224/83469 , H01L2224/83815 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01047 , H01L2924/01048 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/1461 , H01L2924/17738 , H01L2924/17747 , H01L2924/1776 , H01L2924/00014 , H01L2924/01074 , H01L2924/01023 , H01L2924/01015 , H01L2924/00

Abstract: The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Abstract translation: 电子设备包括载体，附着到载体的半导体衬底以及设置在半导体衬底和载体之间的层系统。层系统包括设置在半导体衬底上的电接触层。功能层设置在电接触层上。粘附层设置在功能层上。在粘合层和载体之间设置焊料层。

6.

发明公开
SOCKET INTERFACE FRAMES FOR DEVICES WITH IMPROVED-PERFORMANCE SUBSTRATES 审中-公开

公开(公告)号：US20240222288A1

公开(公告)日：2024-07-04

申请号：US18090140

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： David Shia , Timothy Gosselin , Aravindha Antoniswamy , Sergio Antonio Chan Arguedas , Elah Bozorg-Grayeli , Johnny Cook, JR. , Steven Klein , Rick Canham

IPC: H01L23/544 , H01L23/00 , H01L23/427 , H01L23/49

CPC classification number: H01L23/544 , H01L23/427 , H01L23/49 , H01L24/08 , H01L24/48 , H01L2224/08113 , H01L2224/48229 , H01L2924/15165 , H01L2924/1711 , H01L2924/173 , H01L2924/17724 , H01L2924/1776

Abstract: Integrated circuit (IC) device substrates and structures for mating and aligning with sockets. An IC device may include a frame on and around a substrate, which may include glass or silicon. The frame may include an alignment feature, such as a notch or hole, to mate with a complementary keying feature of a socket. A heat spreader may be coupled to an IC die and extend beyond the substrate or be coupled to the frame. The heat spreader may include a heat pipe. The IC device may be part of an IC system with the device substrate coupled to a system substrate by a socket configured to mate to the frame.