公开(公告)号：US08716068B2

公开(公告)日：2014-05-06

申请号：US14040089

申请日：2013-09-27

Applicant: Texas Instruments Incorporated

Inventor： Darvin R. Edwards ,  Siva P. Gurrum ,  Masood Murtuza ,  Matthew D. Romig ,  Kazunori Hayata

IPC: H01L21/50

CPC classification number: H01L21/56 ,  H01L21/4821 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48639 ,  H01L2224/48739 ,  H01L2224/48839 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/83101 ,  H01L2224/83855 ,  H01L2224/85001 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/12044 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In fabricating a semiconductor device first layers are formed of sintered bondable and solderable metal on a carrier strip. The first layers are patterned into first pads and second pads. A set of first pads is surrounding each second pad. The first pads are spaced from the second pad by gaps. The patterned layers are formed of agglomerate metal vertically on the first layers of sintered bondable and solderable metal of the first pads and of the second pad. The second layers are formed of sintered bondable and solderable metal vertically on the layers of agglomerate metal of the first pads.

Abstract translation: 在制造半导体器件中，第一层由载体条上的可烧结的可焊接金属形成。 第一层被图案化成第一衬垫和第二衬垫。 一组第一焊盘围绕每个第二焊盘。 第一焊盘通过间隙与第二焊盘间隔开。 图案化的层由第一焊盘和第二焊盘的可烧结的可焊接和可焊接金属的第一层上垂直形成为聚集体金属。 第二层由可烧结的可焊接和可焊接的金属垂直地形成在第一焊盘的附聚金属层上。

公开(公告)号：US09373572B2

公开(公告)日：2016-06-21

申请号：US14879622

申请日：2015-10-09

Applicant: Texas Instruments Incorporated

Inventor： Gregory E. Howard ,  Bernardo Gallegos ,  Rajiv Dunne ,  Darvin R. Edwards ,  Siva P. Gurrum ,  Manu J. Prakuzhy ,  Donald C. Abbott

IPC: H01L23/02 ,  H01L23/495 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49589 ,  H01L21/4821 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/17724 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal.

Abstract translation: 一种封装半导体器件，包括引线框和多个角形电容器。 引线框架包括具有表面和侧壁的结构。 角形电容器附接到引线框结构的表面部分。 角形电容器具有与结构侧壁共面的侧壁。 角形电容器包括附着到结构表面的导电材料。 导电材料具有被氧化物覆盖并填充有导电聚合物的孔。 由电极顶起的角形电容器由第二金属制成。

公开(公告)号：US09165873B1

公开(公告)日：2015-10-20

申请号：US14494916

申请日：2014-09-24

Applicant: Texas Instruments Incorporated

Inventor： Gregory E. Howard ,  Bernardo Gallegos ,  Rajiv Dunne ,  Darvin R. Edwards ,  Siva P. Gurrum ,  Manu J. Prakuzhy ,  Donald C. Abbott

IPC: H01L23/02 ,  H01L23/495

CPC classification number: H01L23/49589 ,  H01L21/4821 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/17724 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A packaged semiconductor device including a leadframe made of a first metal, the leadframe including structures with surfaces and sidewalls; capacitors attached to surface portions of the leadframe structures, the capacitors having sidewalls coplanar with structure sidewalls; the capacitors including a foil of conductive material attached to the structure surface, the conductive material having pores covered by oxide and filled with conductive polymer, the capacitors topped by electrodes made of a second metal.

Abstract translation: 一种封装半导体器件，包括由第一金属制成的引线框架，所述引线框架包括具有表面和侧壁的结构; 电容器附接到引线框架结构的表面部分，电容器具有与结构侧壁共面的侧壁; 所述电容器包括附着到所述结构表面的导电材料箔，所述导电材料具有由氧化物覆盖并填充有导电聚合物的孔，所述电容器由由第二金属制成的电极顶起。

公开(公告)号：US20140038358A1

公开(公告)日：2014-02-06

申请号：US14040089

申请日：2013-09-27

Applicant: Texas Instruments Incorporated

Inventor： Darvin R. Edwards ,  Siva P. Gurrum ,  Masood Murtuza ,  Matthew D. Romig ,  Kazunori HAYATA

IPC: H01L21/56

CPC classification number: H01L21/56 ,  H01L21/4821 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48639 ,  H01L2224/48739 ,  H01L2224/48839 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/83101 ,  H01L2224/83855 ,  H01L2224/85001 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/12044 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In fabricating a semiconductor device first layers are formed of sintered bondable and solderable metal on a carrier strip. The first layers are patterned into first pads and second pads. A set of first pads is surrounding each second pad. The first pads are spaced from the second pad by gaps. The patterned layers are formed of agglomerate metal vertically on the first layers of sintered bondable and solderable metal of the first pads and of the second pad. The second layers are formed of sintered bondable and solderable metal vertically on the layers of agglomerate metal of the first pads

Abstract translation: 在制造半导体器件中，第一层由载体条上的可烧结的可焊接金属形成。 第一层被图案化成第一衬垫和第二衬垫。 一组第一焊盘围绕每个第二焊盘。 第一焊盘通过间隙与第二焊盘间隔开。 图案化的层由第一焊盘和第二焊盘的可烧结的可焊接和可焊接金属的第一层上垂直形成为聚集体金属。 第二层由可烧结的可焊接和可焊接的金属垂直地形成在第一焊盘的附聚金属层上

公开(公告)号：US20160035655A1

公开(公告)日：2016-02-04

申请号：US14879622

申请日：2015-10-09

Applicant: Texas Instruments Incorporated

Inventor： Gregory E. Howard ,  Bernardo Gallegos ,  Rajiv Dunne ,  Darvin R. Edwards ,  Siva P. Gurrum ,  Manu J. Prakuzhy ,  Donald C. Abbott

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49589 ,  H01L21/4821 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/17724 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal.

Abstract translation: 一种封装半导体器件，包括引线框和多个角形电容器。 引线框架包括具有表面和侧壁的结构。 角形电容器附接到引线框结构的表面部分。 角形电容器具有与结构侧壁共面的侧壁。 角形电容器包括附着到结构表面的导电材料。 导电材料具有被氧化物覆盖并填充有导电聚合物的孔。 由电极顶起的角形电容器由第二金属制成。

公开(公告)号：US09142496B1

公开(公告)日：2015-09-22

申请号：US14444370

申请日：2014-07-28

Applicant: Texas Instruments Incorporated

Inventor： Gregory E. Howard ,  Bernardo Gallegos ,  Rajiv Dunne ,  Darvin R. Edwards ,  Siva P. Gurrum ,  Manu J. Prakuzhy ,  Donald C. Abbott

IPC: H01L21/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/49589 ,  H01L21/4821 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a packaged semiconductor device begins by placing a first mask on a foil of porous conductive material bonded on a strip of a first metal. The surface of the conductive material and the inside of the pores are oxidized. The first mask leaves areas unprotected. The pores of the unprotected areas are filled with a conductive polymeric compound. A layer of a second metal is deposited on the conductive polymeric compound in the unprotected areas. The first mask is removed to expose un-oxidized conductive material. The foil thickness of the un-oxidized conductive material is removed to expose the underlying first metal. This creates sidewalls of the foil and leaves un-removed the capacitor areas covered by the second metal. A second mask is placed on the strip, the second mask defines a plurality of leadframes having chip pads and leads, and protecting the capacitor areas. The portions of the first metal exposed by the second mask are removed. Sidewalls of the first metal are coplanar with the foil sidewalls. The second mask is removed.

Abstract translation: 一种用于制造封装半导体器件的方法开始于将第一掩模放置在结合在第一金属条带上的多孔导电材料箔上。 导电材料的表面和孔的内部被氧化。 第一个面罩不保护区域。 未保护区域的孔填充有导电聚合物。 一层第二金属沉积在未保护区域的导电聚合物上。 去除第一个掩模以暴露未氧化的导电材料。 去除未氧化的导电材料的箔厚度以暴露下面的第一金属。 这产生了箔的侧壁，并且未去除由第二金属覆盖的电容器区域。 第二掩模被放置在条上，第二掩模限定具有芯片焊盘和引线的多个引线框架，并保护电容器区域。 去除由第二掩模曝光的第一金属的部分。 第一金属的侧壁与箔侧壁共面。 第二个面具被删除。