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    Semiconductor package having etched foil capacitor integrated into leadframe
    1.
    发明授权
    Semiconductor package having etched foil capacitor integrated into leadframe 有权
    具有集成到引线框架中的蚀刻箔电容器的半导体封装

    公开(公告)号：US09142496B1

    公开(公告)日：2015-09-22

    申请号：US14444370

    申请日：2014-07-28

    Applicant: Texas Instruments Incorporated

    Inventor： Gregory E. Howard ,  Bernardo Gallegos ,  Rajiv Dunne ,  Darvin R. Edwards ,  Siva P. Gurrum ,  Manu J. Prakuzhy ,  Donald C. Abbott

    IPC: H01L21/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/56 ,  H01L21/48

    CPC classification number: H01L23/49589 ,  H01L21/4821 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for fabricating a packaged semiconductor device begins by placing a first mask on a foil of porous conductive material bonded on a strip of a first metal. The surface of the conductive material and the inside of the pores are oxidized. The first mask leaves areas unprotected. The pores of the unprotected areas are filled with a conductive polymeric compound. A layer of a second metal is deposited on the conductive polymeric compound in the unprotected areas. The first mask is removed to expose un-oxidized conductive material. The foil thickness of the un-oxidized conductive material is removed to expose the underlying first metal. This creates sidewalls of the foil and leaves un-removed the capacitor areas covered by the second metal. A second mask is placed on the strip, the second mask defines a plurality of leadframes having chip pads and leads, and protecting the capacitor areas. The portions of the first metal exposed by the second mask are removed. Sidewalls of the first metal are coplanar with the foil sidewalls. The second mask is removed.

    Abstract translation: 一种用于制造封装半导体器件的方法开始于将第一掩模放置在结合在第一金属条带上的多孔导电材料箔上。 导电材料的表面和孔的内部被氧化。 第一个面罩不保护区域。 未保护区域的孔填充有导电聚合物。 一层第二金属沉积在未保护区域的导电聚合物上。 去除第一个掩模以暴露未氧化的导电材料。 去除未氧化的导电材料的箔厚度以暴露下面的第一金属。 这产生了箔的侧壁，并且未去除由第二金属覆盖的电容器区域。 第二掩模被放置在条上，第二掩模限定具有芯片焊盘和引线的多个引线框架，并保护电容器区域。 去除由第二掩模曝光的第一金属的部分。 第一金属的侧壁与箔侧壁共面。 第二个面具被删除。

    Copper leadframe finish for copper wire bonding
    2.
    发明授权
    Copper leadframe finish for copper wire bonding 有权
    用于铜线接合的铜引线框完成

    公开(公告)号：US09059185B2

    公开(公告)日：2015-06-16

    申请号：US13939328

    申请日：2013-07-11

    Applicant: Texas Instruments Incorporated

    Inventor： Donald C. Abbott

    IPC: H01L21/82 ,  H01L21/56

    CPC classification number: H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753

    Abstract: A semiconductor device (100) includes a leadframe having a chip pad (110) and a lead (111) with a first end (112) proximate to the pad and a second end (113) remote from the pad, the leadframe having a base metal (120) including copper and a stack of a plated first layer (121) of nickel in contact with the base metal and a plated second layer (122) of a noble metal in contact with the nickel layer, the second lead end free of the noble metal. Further included is a copper wire (104) having a ball bond (104a) on a semiconductor chip (101) attached to the chip pad, and a stitch bond (104b) on the proximate lead end, the stitch bond penetrating the second layer; furthermore a packaging compound (130) encapsulating the chip, the wire, and the first end of the lead, the compound leaving the second end of the lead un-encapsulated; and the unencapsulated second lead end covered with a plated third layer (123) of solder.

    Abstract translation: 半导体器件（100）包括具有芯片焊盘（110）和引线（111）的引线框架，引线（111）具有靠近焊盘的第一端（112）和远离焊盘的第二端（113），引线框架具有基座 包括铜的金属（120）和与基底金属接触的镀覆的第一层（121）的叠层和与镍层接触的贵金属的镀覆的第二层（122），第二引线端没有 贵金属。 还包括在安装在芯片焊盘上的半导体芯片（101）上具有球接合（104a）的铜线（104），以及紧邻引线端上的针脚接合（104b），该线圈键穿透第二层; 此外，封装芯片，导线和引线的第一端的封装化合物（130），离开引线的第二端的化合物未封装; 并且未封装的第二引线端覆盖有镀覆的第三层焊料（123）。

    Selective planishing method for making a semiconductor device
    3.
    发明授权
    Selective planishing method for making a semiconductor device 有权

    公开(公告)号：US10438816B2

    公开(公告)日：2019-10-08

    申请号：US15913499

    申请日：2018-03-06

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Donald C. Abbott

    IPC: H01L21/48 ,  H01L21/56 ,  H01L21/64 ,  H01L23/495 ,  H01L23/00

    Abstract: In a method for fabricating semiconductor devices a leadframe pattern is formed from a flat tape of base metal. A plurality of additional metal layers is plated on the patterned tape of base metal. The surface of the metal layers is roughed. A plurality of sites for assembling semiconductor chips are created. The sites alternate with zones for connecting the leadframe pattern to molding compound runners A selected first set of leadframe areas are selectively planished creating flattened areas offsetting a second set of leadframe areas. A semiconductor chip is attached to each site.

    Semiconductor device with selective planished leadframe
    4.
    发明授权
    Semiconductor device with selective planished leadframe 有权
    具有选择性平面引线框的半导体器件

    公开(公告)号：US08963300B2

    公开(公告)日：2015-02-24

    申请号：US14066885

    申请日：2013-10-30

    Applicant: Texas Instruments Incorporated

    Inventor： Donald C. Abbott

    IPC: H01L23/495 ,  H01L21/48 ,  H01L21/64

    CPC classification number: H01L21/4842 ,  H01L21/4821 ,  H01L21/561 ,  H01L21/64 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49565 ,  H01L23/49575 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/181 ,  H01L2924/2064 ,  Y10T29/49121 ,  H01L2924/00 ,  H01L2224/45099

    Abstract: A semiconductor device includes a leadframe, a semiconductor chip, a packaging compound. The leadframe has a pad with straps. Leads on the leadframe include first and second portions. The pad, the straps, and the leads have a mechanically rough surface. The semiconductor chip is attached to the pad and wire bonded to the first lead portions. A packaging compound encapsulates the chip, the pad, the straps, the bonding wires and the first lead portions. The second lead portions are left un-encapsulated. The strap ends are exposed on the surface of the package. At least one of the straps includes a portion adjacent to the exposed end. This portion having a mechanically smooth surface transitioning by a step into the rough surface of the remainder of the strap.

    Abstract translation: 半导体器件包括引线框，半导体芯片，封装化合物。 引线框架带有带子的垫子。 引线框上的引线包括第一和第二部分。 垫，带和引线具有机械粗糙的表面。 半导体芯片附接到焊盘，并且引线接合到第一引线部分。 封装组合物封装芯片，焊盘，带，接合线和第一引线部分。 第二引线部分未封装。 带端部暴露在包装的表面上。 带中的至少一个包括与暴露端相邻的部分。 该部分具有机械平滑的表面，通过台阶转移到带的其余部分的粗糙表面。

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