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    SEMICONDUCTOR PACKAGE WITH NICKEL-SILVER PRE-PLATED LEADFRAME
    1.
    发明申请
    SEMICONDUCTOR PACKAGE WITH NICKEL-SILVER PRE-PLATED LEADFRAME 有权

    公开(公告)号：US20220208665A1

    公开(公告)日：2022-06-30

    申请号：US17139985

    申请日：2020-12-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Nazila Dadvand ,  Bernardo Gallegos

    IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

    Abstract: A semiconductor package includes a pad and leads, the pad and leads including a base metal predominantly including copper, a first plated metal layer predominantly including nickel in contact with the base metal, and a second plated metal layer predominantly including silver in contact with the first plated metal layer. The first plated metal layer has a first plated metal layer thickness of 0.1 to 5 microns, and the second plated metal layer has a second plated metal layer thickness of 0.2 to 5 microns. The semiconductor package further includes an adhesion promotion coating predominantly including silver oxide in contact with the second plated metal layer opposite the first plated metal layer, a semiconductor die mounted on the pad, a wire bond extending between the semiconductor die and a lead of the leads, and a mold compound covering the semiconductor die and the wire bond.

    Semiconductor package with nickel-silver pre-plated leadframe
    3.
    发明授权
    Semiconductor package with nickel-silver pre-plated leadframe 有权

    公开(公告)号：US12154845B2

    公开(公告)日：2024-11-26

    申请号：US18389651

    申请日：2023-12-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Nazila Dadvand ,  Bernardo Gallegos

    IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

    Abstract: A semiconductor package includes a pad and leads, the pad and leads including a base metal predominantly including copper, a first plated metal layer predominantly including nickel in contact with the base metal, and a second plated metal layer predominantly including silver in contact with the first plated metal layer. The first plated metal layer has a first plated metal layer thickness of 0.1 to 5 microns, and the second plated metal layer has a second plated metal layer thickness of 0.2 to 5 microns. The semiconductor package further includes an adhesion promotion coating predominantly including silver oxide in contact with the second plated metal layer opposite the first plated metal layer, a semiconductor die mounted on the pad, a wire bond extending between the semiconductor die and a lead of the leads, and a mold compound covering the semiconductor die and the wire bond.

    Semiconductor package having etched foil capacitor integrated into leadframe
    6.
    发明授权
    Semiconductor package having etched foil capacitor integrated into leadframe 有权
    具有集成到引线框架中的蚀刻箔电容器的半导体封装

    公开(公告)号：US09142496B1

    公开(公告)日：2015-09-22

    申请号：US14444370

    申请日：2014-07-28

    Applicant: Texas Instruments Incorporated

    Inventor： Gregory E. Howard ,  Bernardo Gallegos ,  Rajiv Dunne ,  Darvin R. Edwards ,  Siva P. Gurrum ,  Manu J. Prakuzhy ,  Donald C. Abbott

    IPC: H01L21/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/56 ,  H01L21/48

    CPC classification number: H01L23/49589 ,  H01L21/4821 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for fabricating a packaged semiconductor device begins by placing a first mask on a foil of porous conductive material bonded on a strip of a first metal. The surface of the conductive material and the inside of the pores are oxidized. The first mask leaves areas unprotected. The pores of the unprotected areas are filled with a conductive polymeric compound. A layer of a second metal is deposited on the conductive polymeric compound in the unprotected areas. The first mask is removed to expose un-oxidized conductive material. The foil thickness of the un-oxidized conductive material is removed to expose the underlying first metal. This creates sidewalls of the foil and leaves un-removed the capacitor areas covered by the second metal. A second mask is placed on the strip, the second mask defines a plurality of leadframes having chip pads and leads, and protecting the capacitor areas. The portions of the first metal exposed by the second mask are removed. Sidewalls of the first metal are coplanar with the foil sidewalls. The second mask is removed.

    Abstract translation: 一种用于制造封装半导体器件的方法开始于将第一掩模放置在结合在第一金属条带上的多孔导电材料箔上。 导电材料的表面和孔的内部被氧化。 第一个面罩不保护区域。 未保护区域的孔填充有导电聚合物。 一层第二金属沉积在未保护区域的导电聚合物上。 去除第一个掩模以暴露未氧化的导电材料。 去除未氧化的导电材料的箔厚度以暴露下面的第一金属。 这产生了箔的侧壁，并且未去除由第二金属覆盖的电容器区域。 第二掩模被放置在条上，第二掩模限定具有芯片焊盘和引线的多个引线框架，并保护电容器区域。 去除由第二掩模曝光的第一金属的部分。 第一金属的侧壁与箔侧壁共面。 第二个面具被删除。

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