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    SEMICONDUCTOR SUBSTRATE HAVING STRESS-ABSORBING SURFACE LAYER
    2.
    发明申请
    SEMICONDUCTOR SUBSTRATE HAVING STRESS-ABSORBING SURFACE LAYER 有权
    具有应力吸收表面层的半导体衬底

    公开(公告)号：US20150021762A1

    公开(公告)日：2015-01-22

    申请号：US14333553

    申请日：2014-07-17

    Applicant: Texas Instruments Incorporated

    Inventor： Jaimal M. Williamson ,  Nima Shahidi ,  Jose Carlos Arroyo

    IPC: H01L23/00

    CPC classification number: H01L21/563 ,  H01L23/295 ,  H01L23/3135 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/014

    Abstract: An assembly (101) comprising a semiconductor device (110) with solderable bumps (112); a substrate (120) with a layer (130) of a first insulating compound and an underlying metal layer (140) patterned in contact pads (141) and connecting traces (142), the insulating layer having openings (132) to expose the surface (142a) and sidewalls (142b) of underlying traces; the device bumps soldered onto the contact pads, establishing a gap (150) between device and top insulating layer; and a second insulating compound (160) cohesively filling the gap and the second openings, thereby touching the underlying traces, the second insulating compound having a higher glass transition temperature, a higher modulus, and a lower coefficient of thermal expansion than the first insulating compound.

    Abstract translation: 包括具有可焊接凸块（112）的半导体器件（110）的组件（101） 具有第一绝缘化合物的层（130）和在接触焊盘（141）和连接迹线（142）中图案化的下面的金属层（140）的衬底（120），所述绝缘层具有开口（132）以暴露表面 （142a）和下面迹线的侧壁（142b）; 所述器件隆起焊接到所述接触焊盘上，在器件和顶部绝缘层之间建立间隙（150）; 以及第二绝缘化合物（160），其粘合地填充所述间隙和所述第二开口，从而接触下面的迹线，所述第二绝缘化合物具有比所述第一绝缘化合物更高的玻璃化转变温度，更高的模量和更低的热膨胀系数 。

    SEMICONDUCTOR DEVICE ASSEMBLY WITH PRE-REFLOWED SOLDER
    3.
    发明申请
    SEMICONDUCTOR DEVICE ASSEMBLY WITH PRE-REFLOWED SOLDER 有权

    公开(公告)号：US20220122940A1

    公开(公告)日：2022-04-21

    申请号：US17074182

    申请日：2020-10-19

    Applicant: Texas Instruments Incorporated

    Inventor： James Raymond Maliclic Baello ,  Steffany Ann Lacierda Moreno ,  Jose Carlos Arroyo

    IPC: H01L23/00

    Abstract: A semiconductor device assembly includes a package substrate having a top side including a plurality of bondable features, at least one integrated circuit (IC) die including a substrate having at least a semiconductor surface including circuitry configured for realizing at least one function including nodes coupled to bond pads with metal posts on the bond pads. The metal posts are attached by a solder joint to the bondable features. The solder joint has a void density of less than or equal to (≥) 5% of a cross-sectional area of the solder joint.

    Semiconductor substrate having stress-absorbing surface layer
    4.
    发明授权
    Semiconductor substrate having stress-absorbing surface layer 有权

    公开(公告)号：US10347589B2

    公开(公告)日：2019-07-09

    申请号：US15498461

    申请日：2017-04-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jaimal M. Williamson ,  Nima Shahidi ,  Jose Carlos Arroyo

    IPC: H01L23/48 ,  H01L21/00 ,  H05K7/10 ,  H01L23/00 ,  H01L23/498 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56

    Abstract: An assembly (101) comprising a semiconductor device (110) with solderable bumps (112); a substrate (120) with a layer (130) of a first insulating compound and an underlying metal layer (140) patterned in contact pads (141) and connecting traces (142), the insulating layer having openings (132) to expose the surface (142a) and sidewalls (142b) of underlying traces; the device bumps soldered onto the contact pads, establishing a gap (150) between device and top insulating layer; and a second insulating compound (160) cohesively filling the gap and the second openings, thereby touching the underlying traces, the second insulating compound having a higher glass transition temperature, a higher modulus, and a lower coefficient of thermal expansion than the first insulating compound.

    SEMICONDUCTOR DEVICE ASSEMBLY WITH PRE-REFLOWED SOLDER
    6.
    发明申请
    SEMICONDUCTOR DEVICE ASSEMBLY WITH PRE-REFLOWED SOLDER 有权

    公开(公告)号：US20250022841A1

    公开(公告)日：2025-01-16

    申请号：US18902251

    申请日：2024-09-30

    Applicant: Texas Instruments Incorporated

    Inventor： James Raymond Maliclic Baello ,  Steffany Ann Lacierda Moreno ,  Jose Carlos Arroyo

    IPC: H01L23/00

    Abstract: A semiconductor device assembly includes a package substrate having a top side including a plurality of bondable features, at least one integrated circuit (IC) die including a substrate having at least a semiconductor surface including circuitry configured for realizing at least one function including nodes coupled to bond pads with metal posts on the bond pads. The metal posts are attached by a solder joint to the bondable features. The solder joint has a void density of less than or equal to (≤) 5% of a cross-sectional area of the solder joint.

    MICROELECTRONICS DEVICE PACKAGE AND METHODS
    10.
    发明公开
    MICROELECTRONICS DEVICE PACKAGE AND METHODS 审中-公开

    公开(公告)号：US20230411262A1

    公开(公告)日：2023-12-21

    申请号：US18335979

    申请日：2023-06-15

    Applicant: Texas Instruments Incorporated

    Inventor： Osvaldo Lopez ,  Jonathan Noquil ,  Jose Carlos Arroyo ,  Makarand R. Kulkarni ,  Guangxu Li

    IPC: H01L23/498 ,  H01L21/56

    CPC classification number: H01L23/49811 ,  H01L21/565 ,  H01L2021/60022 ,  H01L23/49822 ,  H01L21/563

    Abstract: An example microelectronics device package includes: a device mounting layer on an uppermost trace conductor layer on a device side surface of a package substrate, the uppermost trace conductor layer having a first pattern density. The device mounting layer includes a device connection conductor layer; a device mounting land conductor layer on the device connection conductor layer, the device mounting land conductor layer having device mounting land conductors directly contacting the conductors of the device connection conductor layer and having a second pattern density that is less than the first pattern density. A semiconductor die is flip chip mounted to the device mounting layer by solder joints between post connects extending from the semiconductor die and the device mounting land conductors. Mold compound covers the semiconductor die, and the device mounting layer, the mold compound is spaced from the uppermost trace conductor layer by the device mounting layer.

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