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    Semiconductor substrate having stress-absorbing surface layer
    1.
    发明授权
    Semiconductor substrate having stress-absorbing surface layer 有权

    公开(公告)号：US10347589B2

    公开(公告)日：2019-07-09

    申请号：US15498461

    申请日：2017-04-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jaimal M. Williamson ,  Nima Shahidi ,  Jose Carlos Arroyo

    IPC: H01L23/48 ,  H01L21/00 ,  H05K7/10 ,  H01L23/00 ,  H01L23/498 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56

    Abstract: An assembly (101) comprising a semiconductor device (110) with solderable bumps (112); a substrate (120) with a layer (130) of a first insulating compound and an underlying metal layer (140) patterned in contact pads (141) and connecting traces (142), the insulating layer having openings (132) to expose the surface (142a) and sidewalls (142b) of underlying traces; the device bumps soldered onto the contact pads, establishing a gap (150) between device and top insulating layer; and a second insulating compound (160) cohesively filling the gap and the second openings, thereby touching the underlying traces, the second insulating compound having a higher glass transition temperature, a higher modulus, and a lower coefficient of thermal expansion than the first insulating compound.

    Integrated circuit package and method of manufacture
    4.
    发明授权
    Integrated circuit package and method of manufacture 有权
    集成电路封装及制造方法

    公开(公告)号：US09281269B2

    公开(公告)日：2016-03-08

    申请号：US13682576

    申请日：2012-11-20

    Applicant: Texas Instruments Incorporated

    Inventor： Jaimal Mallory Williamson ,  Nima Shahidi ,  Yaoyu Pang

    IPC: H01L23/48 ,  H01L23/498

    CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/014

    Abstract: An integrated circuit (IC) package, device, including a substrate having a top surface with an IC die mounting area and a peripheral area surrounding the mounting area, a plurality of parallel conductor layers, a plurality of insulating layers and a plurality of plated through holes (PTHs) extending through the conductor layers and insulating layers. Various substrate structures in which certain of the PTHs and/or conductor layers and/or insulating layers have different CTE's than the others is disclosed. The various structures may reduce circuit failures due to substrate warpage and/or solder joint damage associated with a CTE mismatch between the substrate and the IC die.

    Abstract translation: 一种集成电路（IC）封装，包括具有具有IC管芯安装区域的顶表面和围绕安装区域的周边区域的衬底的器件，多个平行导体层，多个绝缘层和多个电镀通孔 延伸穿过导体层和绝缘层的孔（PTH）。 公开了其中某些PTH和/或导体层和/或绝缘层具有与其它层不同的CTE的各种衬底结构。 由于与基板和IC芯片之间的CTE失配相关联的基板翘曲和/或焊点损伤，各种结构可能减少电路故障。

    Electronic assembly with copper pillar attach substrate
    5.
    发明授权
    Electronic assembly with copper pillar attach substrate 有权
    电子组装与铜柱连接基板

    公开(公告)号：US08896118B2

    公开(公告)日：2014-11-25

    申请号：US13798678

    申请日：2013-03-13

    Applicant: Texas Instruments Incorporated

    Inventor： Nima Shahidi

    IPC: H01L23/48 ,  H01L21/44 ,  H01L23/498 ,  H01L21/48

    CPC classification number: H01L21/4853 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/11

    Abstract: An electronic assembly includes a copper pillar attach substrate that has a dielectric layer and a solder resist layer overlying the dielectric layer. The solder resist layer has a plurality of solder resist openings. A plurality of parallel traces are formed on the dielectric layer. Each trace has a first end portion, a second end portion and an intermediate portion. The first and second end portions of each trace are covered by the solder resist layer and the intermediate portions are positioned in the solder resist openings. Each of the intermediate portions has at least one conductive coating layer on it and has a height measured from the dielectric layer to the top of the topmost conductive coating layer that is at least as great as the solder resist layer thickness.

    Abstract translation: 电子组件包括铜柱附着衬底，其具有覆盖在电介质层上的电介质层和阻焊层。 阻焊层具有多个阻焊剂开口。 在电介质层上形成多个平行迹线。 每个迹线具有第一端部分，第二端部部分和中间部分。 每个迹线的第一和第二端部被阻焊层覆盖，并且中间部分位于阻焊剂开口中。 每个中间部分在其上具有至少一个导电涂层，并且具有至少与阻焊层厚度一样大的从电介质层到顶部导电涂层的顶部的高度。

    Semiconductor Substrate Having Stress-Absorbing Surface Layer
    6.
    发明申请
    Semiconductor Substrate Having Stress-Absorbing Surface Layer 审中-公开

    公开(公告)号：US20190279944A1

    公开(公告)日：2019-09-12

    申请号：US16427150

    申请日：2019-05-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jaimal M. Williamson ,  Nima Shahidi ,  Jose Carlos Arroyo

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56

    Abstract: An assembly (101) comprising a semiconductor device (110) with solderable bumps (112); a substrate (120) with a layer (130) of a first insulating compound and an underlying metal layer (140) patterned in contact pads (141) and connecting traces (142), the insulating layer having openings (132) to expose the surface (142a) and sidewalls (142b) of underlying traces; the device bumps soldered onto the contact pads, establishing a gap (150) between device and top insulating layer; and a second insulating compound (160) cohesively filling the gap and the second openings, thereby touching the underlying traces, the second insulating compound having a higher glass transition temperature, a higher modulus, and a lower coefficient of thermal expansion than the first insulating compound.

    ELECTRONIC ASSEMBLY WITH COPPER PILLAR ATTACH SUBSTRATE
    7.
    发明申请
    ELECTRONIC ASSEMBLY WITH COPPER PILLAR ATTACH SUBSTRATE 有权
    电子组件与铜柱连接基板

    公开(公告)号：US20140264829A1

    公开(公告)日：2014-09-18

    申请号：US13798678

    申请日：2013-03-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Nima Shahidi

    IPC: H01L23/498 ,  H01L21/48

    CPC classification number: H01L21/4853 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/11

    Abstract: An electronic assembly includes a copper pillar attach substrate that has a dielectric layer and a solder resist layer overlying the dielectric layer. The solder resist layer has a plurality of solder resist openings. A plurality of parallel traces are formed on the dielectric layer. Each trace has a first end portion, a second end portion and an intermediate portion. The first and second end portions of each trace are covered by the solder resist layer and the intermediate portions are positioned in the solder resist openings. Each of the intermediate portions has at least one conductive coating layer on it and has a height measured from the dielectric layer to the top of the topmost conductive coating layer that is at least as great as the solder resist layer thickness.

    Abstract translation: 电子组件包括铜柱附着衬底，其具有覆盖在电介质层上的电介质层和阻焊层。 阻焊层具有多个阻焊剂开口。 在电介质层上形成多个平行迹线。 每个迹线具有第一端部分，第二端部部分和中间部分。 每个迹线的第一和第二端部被阻焊层覆盖，并且中间部分位于阻焊剂开口中。 每个中间部分在其上具有至少一个导电涂层，并且具有至少与阻焊层厚度一样大的从电介质层到顶部导电涂层的顶部的高度。

    INTEGRATED CIRCUIT PACKAGE AND METHOD OF MANUFACTURE
    8.
    发明申请
    INTEGRATED CIRCUIT PACKAGE AND METHOD OF MANUFACTURE 有权
    集成电路封装及其制造方法

    公开(公告)号：US20140138822A1

    公开(公告)日：2014-05-22

    申请号：US13682576

    申请日：2012-11-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jaimal Mallory Williamson ,  Nima Shahidi ,  Yaoyu Pang

    IPC: H01L23/498

    CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/014

    Abstract: An integrated circuit (IC) package, device, including a substrate having a top surface with an IC die mounting area and a peripheral area surrounding the mounting area, a plurality of parallel conductor layers, a plurality of insulating layers and a plurality of plated through holes (PTHs) extending through the conductor layers and insulating layers. Various substrate structures in which certain of the PTHs and/or conductor layers and/or insulating layers have different CTE's than the others is disclosed. The various structures may reduce circuit failures due to substrate warpage and/or solder joint damage associated with a CTE mismatch between the substrate and the IC die.

    Abstract translation: 一种集成电路（IC）封装，包括具有具有IC管芯安装区域的顶表面和围绕安装区域的周边区域的衬底的器件，多个平行导体层，多个绝缘层和多个电镀通孔 延伸穿过导体层和绝缘层的孔（PTH）。 公开了其中某些PTH和/或导体层和/或绝缘层具有与其它层不同的CTE的各种衬底结构。 由于与基板和IC芯片之间的CTE失配相关联的基板翘曲和/或焊点损伤，各种结构可能减少电路故障。

    SEMICONDUCTOR SUBSTRATE HAVING STRESS-ABSORBING SURFACE LAYER
    9.
    发明申请
    SEMICONDUCTOR SUBSTRATE HAVING STRESS-ABSORBING SURFACE LAYER 有权
    具有应力吸收表面层的半导体衬底

    公开(公告)号：US20150021762A1

    公开(公告)日：2015-01-22

    申请号：US14333553

    申请日：2014-07-17

    Applicant: Texas Instruments Incorporated

    Inventor： Jaimal M. Williamson ,  Nima Shahidi ,  Jose Carlos Arroyo

    IPC: H01L23/00

    CPC classification number: H01L21/563 ,  H01L23/295 ,  H01L23/3135 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/014

    Abstract: An assembly (101) comprising a semiconductor device (110) with solderable bumps (112); a substrate (120) with a layer (130) of a first insulating compound and an underlying metal layer (140) patterned in contact pads (141) and connecting traces (142), the insulating layer having openings (132) to expose the surface (142a) and sidewalls (142b) of underlying traces; the device bumps soldered onto the contact pads, establishing a gap (150) between device and top insulating layer; and a second insulating compound (160) cohesively filling the gap and the second openings, thereby touching the underlying traces, the second insulating compound having a higher glass transition temperature, a higher modulus, and a lower coefficient of thermal expansion than the first insulating compound.

    Abstract translation: 包括具有可焊接凸块（112）的半导体器件（110）的组件（101） 具有第一绝缘化合物的层（130）和在接触焊盘（141）和连接迹线（142）中图案化的下面的金属层（140）的衬底（120），所述绝缘层具有开口（132）以暴露表面 （142a）和下面迹线的侧壁（142b）; 所述器件隆起焊接到所述接触焊盘上，在器件和顶部绝缘层之间建立间隙（150）; 以及第二绝缘化合物（160），其粘合地填充所述间隙和所述第二开口，从而接触下面的迹线，所述第二绝缘化合物具有比所述第一绝缘化合物更高的玻璃化转变温度，更高的模量和更低的热膨胀系数 。

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