公开(公告)号：US08471382B2

公开(公告)日：2013-06-25

申请号：US13417785

申请日：2012-03-12

Applicant: Kazutaka Takagi

Inventor： Kazutaka Takagi

IPC: H01L23/34

CPC classification number: H01L23/047 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/812 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2223/6633 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13051 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/16195 ,  H01L2924/16747 ,  H01L2924/173 ,  H01L2924/177 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package includes: a metal wall disposed on a conductive base plate; a through-hole disposed in input/output portions of the metal wall; a lower layer feed through disposed on the conductive base plate; a wiring pattern disposed on the lower layer feed through; an upper layer feed through disposed on a part of the lower layer feed through and a part of the wiring pattern; and a terminal disposed on the wiring pattern, wherein a width of a part of the lower layer feed through and a width of the upper layer feed through are wider than a width of the through-hole, the lower layer feed through is adhered to a side surface of the metal wall, the upper layer feed through is adhered to the side surface of metal wall, and an air layer is formed between the wiring pattern and an internal wall of the through-hole.

Abstract translation: 包装包括：设置在导电基板上的金属壁; 设置在金属壁的输入/输出部分中的通孔; 通过设置在导电基板上的下层馈电; 布置在下层上的布线图案馈送; 布置在所述下层的一部分上的上层馈送通过所述布线图案的一部分; 以及设置在布线图案上的端子，其中下层馈送部分的宽度和上层馈送的宽度比通孔的宽度宽，下层馈通被粘附到 金属壁的侧表面，上层进料粘附到金属壁的侧表面，并且在布线图案和通孔的内壁之间形成空气层。

公开(公告)号：US20240312947A1

公开(公告)日：2024-09-19

申请号：US18364893

申请日：2023-08-03

Applicant: Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

Inventor： Tomohiro IGUCHI ,  Tatsuya HIRAKAWA ,  Shogo MINAMI ,  Hiroyuki MATSUO ,  Izuru KOMATSU

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/07

CPC classification number: H01L24/48 ,  H01L23/49811 ,  H01L23/49822 ,  H01L25/072 ,  H01L23/293 ,  H01L2224/48106 ,  H01L2224/48175 ,  H01L2224/48225 ,  H01L2224/48992 ,  H01L2225/04 ,  H01L2924/13091 ,  H01L2924/1659 ,  H01L2924/173 ,  H01L2924/35121

Abstract: A semiconductor device according to an embodiment includes: an insulating substrate having a first metal layer and a second metal layer; a semiconductor chip on the first metal layer having an upper electrode and a lower electrode connected to the first metal layer; a bonding wire having a first end portion connected to the upper electrode and a second end portion connected to the second metal layer; a first resin layer covering the semiconductor chip and the bonding wire, the first resin layer containing a first resin; a second resin layer covering a bonding portion between the first end portion and the upper electrode containing a second resin having a Young's modulus higher than that of the first resin; a third resin layer on the first resin layer, the third resin layer containing a third resin having a moisture permeability lower than that of the first resin.

公开(公告)号：US20180012865A1

公开(公告)日：2018-01-11

申请号：US15203692

申请日：2016-07-06

Applicant: Micron Technology, Inc.

Inventor： Ed A. Schrock

IPC: H01L25/065 ,  H01L23/053 ,  H01L23/31 ,  H01L23/367 ,  H01L23/373 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/4803 ,  H01L21/4817 ,  H01L21/563 ,  H01L21/565 ,  H01L23/053 ,  H01L23/08 ,  H01L23/10 ,  H01L23/24 ,  H01L23/3142 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/4334 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/18 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/29301 ,  H01L2224/29393 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1616 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1715 ,  H01L2924/173 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/0715

Abstract: Several embodiments of the present technology are described with reference to a semiconductor die assembly and processes for manufacturing the assembly. In some embodiments of the present technology, a semiconductor die assembly includes a stack of semiconductor dies attached to a thermal transfer structure (also known as a “heat spreader,” “lid,” or “thermal lid”). The thermal transfer structure conducts heat away from the stack of semiconductor dies. Additionally, the assembly can include molded walls fabricated with molding material to support the thermal transfer structure.

公开(公告)号：US20120126246A1

公开(公告)日：2012-05-24

申请号：US13164155

申请日：2011-06-20

Applicant: Kazutaka TAKAGI

Inventor： Kazutaka TAKAGI

IPC: H01L23/043 ,  H01L29/205 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L23/047 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/812 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2223/6633 ,  H01L2223/6644 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13051 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/16195 ,  H01L2924/16747 ,  H01L2924/173 ,  H01L2924/177 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to one embodiment, provided is a package and high frequency terminal structure for the same including: a conductive base plate; a semiconductor device disposed on the conductive base plate; a metal wall disposed on the conductive base plate to house the semiconductor device; a through-hole disposed in input and output units of the metal wall; a lower layer feed through inserted into the through-hole and disposed on the conductive base plate; and an upper layer feed through disposed on the lower layer feed through, and adhered to a sidewall of the metal wall. The lower layer feed through is surrounded by the metal wall.

Abstract translation: 根据一个实施例，提供了一种用于其的封装和高频端子结构，包括：导电基板; 设置在导电基板上的半导体器件; 设置在所述导电基板上以容纳所述半导体器件的金属壁; 设置在金属壁的输入和输出单元中的通孔; 下层进料通过插入通孔并设置在导电基板上; 并且通过设置在下层上的上层进料通过并附着在金属壁的侧壁上。 下层进料通过金属壁包围。

公开(公告)号：US20240222288A1

公开(公告)日：2024-07-04

申请号：US18090140

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： David Shia ,  Timothy Gosselin ,  Aravindha Antoniswamy ,  Sergio Antonio Chan Arguedas ,  Elah Bozorg-Grayeli ,  Johnny Cook, JR. ,  Steven Klein ,  Rick Canham

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/427 ,  H01L23/49

CPC classification number: H01L23/544 ,  H01L23/427 ,  H01L23/49 ,  H01L24/08 ,  H01L24/48 ,  H01L2224/08113 ,  H01L2224/48229 ,  H01L2924/15165 ,  H01L2924/1711 ,  H01L2924/173 ,  H01L2924/17724 ,  H01L2924/1776

Abstract: Integrated circuit (IC) device substrates and structures for mating and aligning with sockets. An IC device may include a frame on and around a substrate, which may include glass or silicon. The frame may include an alignment feature, such as a notch or hole, to mate with a complementary keying feature of a socket. A heat spreader may be coupled to an IC die and extend beyond the substrate or be coupled to the frame. The heat spreader may include a heat pipe. The IC device may be part of an IC system with the device substrate coupled to a system substrate by a socket configured to mate to the frame.

公开(公告)号：US20150357269A1

公开(公告)日：2015-12-10

申请号：US14706096

申请日：2015-05-07

Applicant: Yunhyeok IM

Inventor： Yunhyeok IM

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/3737 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49816 ,  H01L24/17 ,  H01L25/105 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/173 ,  H01L2924/17724 ,  H01L2924/17747 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a lower package including a lower substrate, a lower semiconductor chip, and a lower molding layer exposing an upper surface of the lower semiconductor chip, bumps on the lower substrate, the bumps being spaced apart from the lower semiconductor chip, a lead frame on the lower semiconductor chip and on the bumps, the lead frame being electrically connected to the bumps and having a thermal conductivity of about 100 W/mk to about 10,000 W/mk, and an upper package on the lead frame and electrically connected to the lead frame.

Abstract translation: 半导体封装包括下封装，其包括下基板，下半导体芯片和暴露下半导体芯片的上表面的下模塑层，下基板上的凸块，凸块与下半导体芯片间隔开， 引线框架在下半导体芯片和凸块上，引线框架电连接到凸块并具有约100W / mk至约10,000W / mk的热导率，以及引线框架上的上封装并电连接 到引线框架。

公开(公告)号：US20150340297A1

公开(公告)日：2015-11-26

申请号：US14695276

申请日：2015-04-24

Applicant: Fuji Electric Co., Ltd.

Inventor： Motohito HORI ,  Yoshikazu TAKAHASHI ,  Yoshinari IKEDA

IPC: H01L23/043 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/492

CPC classification number: H01L23/043 ,  H01L23/051 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/433 ,  H01L23/492 ,  H01L23/49822 ,  H01L24/17 ,  H01L25/072 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1711 ,  H01L2924/1715 ,  H01L2924/173 ,  H01L2924/00

Abstract: A power semiconductor module is equipped with: a frame made of an insulator; a first electrode plate made of a metal and fixed to a bottom opening of the frame; semiconductor chips electrically and physically connected to the first electrode plate; a multilayer substrate fixed to a principal surface of the first electrode plate; wiring members that electrically connect front surface electrodes of the semiconductor chips and a circuit plate of the multilayer substrate; a second electrode plate fixed to a top opening of the frame; and a metal block that has a first surface having a projected portion and a second surface disposed on a side opposite to the first surface and that is tapered from the first surface to the second surface, the projected portion being electrically and physically connected to the circuit plate of the multilayer substrate and the second surface being electrically and physically connected to the second electrode plate.

Abstract translation: 功率半导体模块配备有：由绝缘体制成的框架; 由金属制成的第一电极板，并固定到所述框架的底部开口; 半导体芯片与第一电极板电连接并物理连接; 固定到所述第一电极板的主表面的多层基板; 电连接半导体芯片的前表面电极和多层基板的电路板的布线构件; 固定到所述框架的顶部开口的第二电极板; 以及金属块，其具有第一表面，所述第一表面具有突出部分，所述第二表面设置在与所述第一表面相对的一侧并且从所述第一表面到所述第二表面呈锥形，所述突出部分电连接到所述电路 所述多层基板的所述板和所述第二表面电连接并物理地连接到所述第二电极板。

公开(公告)号：US08637873B2

公开(公告)日：2014-01-28

申请号：US13164155

申请日：2011-06-20

Applicant: Kazutaka Takagi

Inventor： Kazutaka Takagi

IPC: H01L29/04

CPC classification number: H01L23/047 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/812 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2223/6633 ,  H01L2223/6644 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13051 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/16195 ,  H01L2924/16747 ,  H01L2924/173 ,  H01L2924/177 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to one embodiment, provided is a package and high frequency terminal structure for the same including: a conductive base plate; a semiconductor device disposed on the conductive base plate; a metal wall disposed on the conductive base plate to house the semiconductor device; a through-hole disposed in input and output units of the metal wall; a lower layer feed through inserted into the through-hole and disposed on the conductive base plate; and an upper layer feed through disposed on the lower layer feed through, and adhered to a sidewall of the metal wall. The lower layer feed through is surrounded by the metal wall.

Abstract translation: 根据一个实施例，提供了一种用于其的封装和高频端子结构，包括：导电基板; 设置在导电基板上的半导体器件; 设置在所述导电基板上以容纳所述半导体器件的金属壁; 设置在金属壁的输入和输出单元中的通孔; 下层进料通过插入通孔并设置在导电基板上; 并且通过设置在下层上的上层进料通过并附着在金属壁的侧壁上。 下层进料通过金属壁包围。

公开(公告)号：US12119281B2

公开(公告)日：2024-10-15

申请号：US17394093

申请日：2021-08-04

Applicant: Qorvo US, Inc.

Inventor： Dylan Murdock

IPC: H01L23/31 ,  H01L23/04 ,  H01L23/10 ,  H01L23/29 ,  H01L23/00 ,  H01L23/373

CPC classification number: H01L23/3142 ,  H01L23/04 ,  H01L23/10 ,  H01L23/291 ,  H01L23/315 ,  H01L23/3736 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48225 ,  H01L2224/49176 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/0132 ,  H01L2924/01403 ,  H01L2924/05432 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/16747 ,  H01L2924/1676 ,  H01L2924/173 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/3512

Abstract: The present disclosure relates to a hermetic package capable of handling a high coefficient of thermal expansion (CTE) mismatch configuration. The disclosed hermetic package includes a metal base and multiple segments that are discrete from each other. Herein, a gap exists between every two adjacent ceramic wall segments and is sealed with a connecting material. The ceramic wall segments with the connecting material form a ring wall, where the gap between every two adjacent ceramic wall segments is located at a corner of the ring wall. The metal base is either surrounded by the ring wall or underneath the ring wall.

公开(公告)号：US20240038619A1

公开(公告)日：2024-02-01

申请号：US17876621

申请日：2022-07-29

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Kwang-Soo Kim ,  Vivek Arora

IPC: H01L23/367 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/373

CPC classification number: H01L23/3675 ,  H01L24/83 ,  H01L24/32 ,  H01L21/4882 ,  H01L23/5389 ,  H01L23/3735 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/3512 ,  H01L2924/1711 ,  H01L2924/172 ,  H01L2924/173 ,  H01L2924/176 ,  H01L2924/1033 ,  H01L2224/83862 ,  H01L2224/3201 ,  H01L2224/83203

Abstract: An electronic device includes an embedded die frame having a cavity and a routing structure, a semiconductor die in the cavity with a gallium nitride layer on the routing structure, and a heat spreader having a thermally conductive insulator layer and a metal plate, the thermally conductive insulator layer having a first side that faces the embedded die frame and an opposite second side that faces away from the embedded die frame, with a portion of the first side of the thermally conductive insulator layer extending over a side of a silicon substrate of the semiconductor die, and the metal plate on the second side of the thermally conductive insulator layer.