公开(公告)号：US20210013138A1

公开(公告)日：2021-01-14

申请号：US16504816

申请日：2019-07-08

申请人： Texas Instruments Incorporated

发明人： Woochan Kim ,  Vivek Arora ,  Ken Pham

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L23/64 ,  H01L21/48 ,  H01L21/56

摘要： A stacked die semiconductor package includes a leadframe including a die pad and lead terminals on at least two sides of the die pad, a top die having circuitry coupled to bond pads, and bottom die having a back side that is attached by die attach material to the die pad and a top side having at least one redistribution layer (RDL) over and coupled to a top metal level including connections to input/output (IO) nodes on the top metal level. The RDL provides a metal pattern including wirebond pads that match locations of the bond pads of the top die. The bond pads on the top die are flip-chip attached to the wirebond pads of the bottom die, and the bond wires are positioned between the wirebond pads and the lead terminals.

公开(公告)号：US10748827B2

公开(公告)日：2020-08-18

申请号：US16120922

申请日：2018-09-04

申请人： Texas Instruments Incorporated

发明人： Woochan Kim ,  Vivek Arora ,  Anindya Poddar

IPC分类号： H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/56

摘要： In a described example a device includes: a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface; a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall; a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; and portions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer.

公开(公告)号：US20240170359A1

公开(公告)日：2024-05-23

申请号：US17992990

申请日：2022-11-23

申请人： Texas Instruments Incorporated

发明人： Kwang-Soo Kim ,  Vivek Arora

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

CPC分类号： H01L23/3672 ,  H01L21/4875 ,  H01L23/3121 ,  H01L23/49568 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/48175 ,  H01L2224/85007

摘要： An electronic device includes a package structure, a lead, a heat slug, a semiconductor die, and a bond wire. The package structure has opposite first and second sides, and opposite third and fourth sides spaced along a first direction. The heat slug has a first portion partially exposed outside the second side of the package structure, and a second portion with slots extending inwardly along the first direction and fins between respective pairs of the slots, where the fins are enclosed by the package structure and spaced along an orthogonal second direction. The semiconductor die is attached to the heat slug, and the bond wire has a first end connected to the lead and a second end connected to a circuit of the semiconductor die.

公开(公告)号：US11908834B2

公开(公告)日：2024-02-20

申请号：US17741402

申请日：2022-05-10

申请人： Texas Instruments Incorporated

发明人： Vivek Arora ,  Woochan Kim

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/492 ,  H01L23/495 ,  H01L21/56 ,  H01F27/40 ,  H01F27/06 ,  H01L25/00

CPC分类号： H01L25/0655 ,  H01F27/06 ,  H01F27/40 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/4924 ,  H01L23/49503 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/48195 ,  H01L2224/92247

摘要： A multi-chip isolation (ISO) device package includes a leadframe including leads, an interposer substrate including a top copper layer and a bottom metal layer, with a dielectric layer in-between. A first IC die and a second IC die include circuitry including a transmitter or a receiver, and first and second bond pads are both attached top side up in the package. A laminate transformer is attached to the top copper layer positioned lateral to the IC die. Bondwires wirebond the first bond pads to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to a second group of the leads or the lead terminals. A mold compound provides encapsulation.

公开(公告)号：US20220271008A1

公开(公告)日：2022-08-25

申请号：US17741402

申请日：2022-05-10

申请人： Texas Instruments Incorporated

发明人： Vivek Arora ,  Woochan Kim

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/492 ,  H01L23/495 ,  H01L21/56 ,  H01F27/40 ,  H01F27/06 ,  H01L25/00

摘要： A multi-chip isolation (ISO) device package includes a leadframe including leads, an interposer substrate including a top copper layer and a bottom metal layer, with a dielectric layer in-between. A first IC die and a second IC die include circuitry including a transmitter or a receiver, and first and second bond pads are both attached top side up in the package. A laminate transformer is attached to the top copper layer positioned lateral to the IC die. Bondwires wirebond the first bond pads to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to a second group of the leads or the lead terminals. A mold compound provides encapsulation.

公开(公告)号：US11417579B2

公开(公告)日：2022-08-16

申请号：US16996742

申请日：2020-08-18

申请人： Texas Instruments Incorporated

发明人： Woochan Kim ,  Vivek Arora ,  Anindya Poddar

IPC分类号： H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/56

摘要： In a described example a device includes: a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface; a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall; a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; and portions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer.

公开(公告)号：US20200075441A1

公开(公告)日：2020-03-05

申请号：US16120922

申请日：2018-09-04

申请人： Texas Instruments Incorporated

发明人： Woochan Kim ,  Vivek Arora ,  Anindya Poddar

IPC分类号： H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/56

摘要： In a described example a device includes: a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface; a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall; a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; and portions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer.

公开(公告)号：US20240120308A1

公开(公告)日：2024-04-11

申请号：US17960871

申请日：2022-10-06

申请人： Texas Instruments Incorporated

发明人： Kwang-Soo Kim ,  Makoto Shibuya ,  Woochan Kim ,  Vivek Arora

IPC分类号： H01L23/00 ,  H01L25/16

CPC分类号： H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L24/84 ,  H01L25/16 ,  H01L2224/4001 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/4103 ,  H01L2224/41052 ,  H01L2224/41175 ,  H01L2224/48157 ,  H01L2224/73221 ,  H01L2224/84815 ,  H01L2924/1033 ,  H01L2924/1426 ,  H01L2924/19041 ,  H01L2924/30107

摘要： An electronic device includes a substrate having first and second conductive traces, a semiconductor die having a transistor with a first terminal and a second terminal, and first and second metal clips. The first metal clip has a first end portion coupled to the first terminal of the transistor, and a second end portion coupled to the first conductive trace of the substrate. The second metal clip has a first end portion coupled to the second terminal of the transistor and a second end portion coupled to the second conductive trace of the substrate, and a middle portion of the second metal clip is spaced apart from and at least partially overlying a portion of the first metal clip.

公开(公告)号：US11870341B2

公开(公告)日：2024-01-09

申请号：US17677072

申请日：2022-02-22

申请人： Texas Instruments Incorporated

发明人： Yi Yan ,  Vivek Arora

IPC分类号： H02M3/00 ,  H02M3/335 ,  H01F41/02 ,  H01F27/30 ,  H05K7/20

CPC分类号： H02M3/003 ,  H01F27/30 ,  H01F41/0246 ,  H02M3/33523 ,  H05K7/2089

摘要： An isolated power converter package includes a leadframe including a first and second die pad, first and second supports connected to first leads, second leads. A first semiconductor die is on the first die pad and a second semiconductor die is on the second die pad. The molded transformer includes a top and bottom side magnetic sheet each having a magnetic mold material including magnetic particles in a second dielectric material on respective sides of a laminate substrate including a dielectric material and a first coil and a second coil that each include a coil contact. Edges of the laminate substrate are on the supports. Bond wires are between the first die bond pads and the second leads, between the second die bond pads and the second leads, between the first die bond pads and coil contacts, and between the second die bond pads and the coil contacts.

公开(公告)号：US20230268826A1

公开(公告)日：2023-08-24

申请号：US17677072

申请日：2022-02-22

申请人： Texas Instruments Incorporated

发明人： Yi Yan ,  Vivek Arora

IPC分类号： H02M3/00 ,  H02M3/335 ,  H05K7/20 ,  H01F27/30 ,  H01F41/02

CPC分类号： H02M3/003 ,  H02M3/33523 ,  H05K7/2089 ,  H01F27/30 ,  H01F41/0246

摘要： An isolated power converter package includes a leadframe including a first and second die pad, first and second supports connected to first leads, second leads. A first semiconductor die is on the first die pad and a second semiconductor die is on the second die pad. The molded transformer includes a top and bottom side magnetic sheet each having a magnetic mold material including magnetic particles in a second dielectric material on respective sides of a laminate substrate including a dielectric material and a first coil and a second coil that each include a coil contact. Edges of the laminate substrate are on the supports. Bond wires are between the first die bond pads and the second leads, between the second die bond pads and the second leads, between the first die bond pads and coil contacts, and between the second die bond pads and the coil contacts.