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61 条记录 (耗时 0.023 秒)

    SEMICONDUCTOR PACKAGE WITH RAISED DAM ON CLIP OR LEADFRAME
    3.
    发明申请
    SEMICONDUCTOR PACKAGE WITH RAISED DAM ON CLIP OR LEADFRAME 有权

    公开(公告)号：US20230038411A1

    公开(公告)日：2023-02-09

    申请号：US17392738

    申请日：2021-08-03

    申请人： Texas Instruments Incorporated

    发明人： Makoto Shibuya

    IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L23/10 ,  H01L21/56

    摘要： A semiconductor package includes a semiconductor die including circuitry electrically coupled to bond pads that is mounted onto a leadframe. The leadframe includes a plurality of leads and a dam bar having a transverse portion that extends between adjoining ones of the leads. The bond pads are electrically connected to the plurality of leads. A raised dam pattern is on the dam bar or on an edge of an exposed portion of a top side clip of the semiconductor package that is positioned above and connects to the semiconductor die. The raised dam pattern includes a first material that is different relative to the material of the dam bar or the clip. A mold material encapsulates the semiconductor die.

    PACKAGE WITH DIES MOUNTED ON OPPOSING SURFACES OF A LEADFRAME
    5.
    发明申请
    PACKAGE WITH DIES MOUNTED ON OPPOSING SURFACES OF A LEADFRAME 有权

    公开(公告)号：US20210375730A1

    公开(公告)日：2021-12-02

    申请号：US17399018

    申请日：2021-08-10

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Makoto Shibuya ,  Noboru Nakanishi

    IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48

    摘要： A package includes a leadframe having first surface and a second surface opposing the first surface, the leadframe forming a plurality of leads, a first semiconductor die mounted on the first surface of the leadframe and electrically connected to at least one of the plurality of leads, a second semiconductor die mounted on the second surface of the leadframe, wire bonds electrically connecting the second semiconductor die to the leadframe, and mold compound at least partially covering the first semiconductor die, the second semiconductor die and the wire bonds.

    METHODS AND APPARATUS FOR AN IMPROVED INTEGRATED CIRCUIT PACKAGE
    6.
    发明申请
    METHODS AND APPARATUS FOR AN IMPROVED INTEGRATED CIRCUIT PACKAGE 有权

    公开(公告)号：US20210265214A1

    公开(公告)日：2021-08-26

    申请号：US17317845

    申请日：2021-05-11

    申请人： Texas Instruments Incorporated

    发明人： Makoto Shibuya

    IPC分类号： H01L21/78 ,  H01L23/00 ,  H01L23/495 ,  H01L21/48 ,  H01L23/31

    摘要： In a described example, an integrated circuit (IC) package includes an IC die disposed on a die attach pad; a plurality of leads electrically connected to terminals on the IC die, the leads including a base metal; and molding compound material encapsulating portions of the IC die, the die attach pads, and the plurality of leads; the plurality of leads having a solder joint reinforcement tab. The solder joint reinforcement tabs include a first side, a second side opposite to the first side, a third side, a fourth side opposite to and in parallel to the third side, a fifth side forming an end portion of the solder joint reinforcement tab, the solder joint reinforcement tabs including a solderable metal layer on the second, third and fourth sides and on portions of the fifth side.

    Methods and apparatus for an improved integrated circuit package
    7.
    发明授权
    Methods and apparatus for an improved integrated circuit package 有权

    公开(公告)号：US11004742B2

    公开(公告)日：2021-05-11

    申请号：US15462881

    申请日：2017-03-19

    申请人： Texas Instruments Incorporated

    发明人： Makoto Shibuya

    IPC分类号： H01L23/495 ,  H01L21/78 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

    摘要： In a described example, an integrated circuit (IC) package includes an IC die disposed on a die attach pad; a plurality of leads electrically connected to terminals on the IC die, the leads including a base metal; and molding compound material encapsulating portions of the IC die, the die attach pads, and the plurality of leads; the plurality of leads having a solder joint reinforcement tab. The solder joint reinforcement tabs include a first side, a second side opposite to the first side, a third side, a fourth side opposite to and in parallel to the third side, a fifth side forming an end portion of the solder joint reinforcement tab, the solder joint reinforcement tabs including a solderable metal layer on the second, third and fourth sides and on portions of the fifth side.

    WAFER CHIP SCALE PACKAGING WITH BALL ATTACH BEFORE REPASSIVATION
    9.
    发明申请
    WAFER CHIP SCALE PACKAGING WITH BALL ATTACH BEFORE REPASSIVATION 审中-公开

    公开(公告)号：US20200043778A1

    公开(公告)日：2020-02-06

    申请号：US16051590

    申请日：2018-08-01

    申请人： Texas Instruments Incorporated

    发明人： Daiki Komatsu ,  Makoto Shibuya

    IPC分类号： H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/538

    摘要： Disclosed examples provide methods that include forming a conductive structure at least partially above a conductive feature of a wafer, attaching a solder ball structure to a side of the conductive structure, and thereafter forming a repassivation layer on a side of the wafer proximate the side of the conductive structure. Further examples provide microelectronic devices and integrated circuits that include a conductive structure coupled with a conductive feature of a metallization structure, a solder ball structure connected to the conductive structure, and a printed repassivation layer disposed on the side of the metallization structure proximate a side of the conductive structure.