公开(公告)号：US20240222237A1

公开(公告)日：2024-07-04

申请号：US18603047

申请日：2024-03-12

Applicant: Texas Instruments Incorporated

Inventor： Vivek K. Arora ,  Woochan Kim

IPC: H01L23/495 ,  H01F27/28 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373

CPC classification number: H01L23/49575 ,  H01F27/2804 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3738 ,  H01L23/49513 ,  H01L23/49562 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01F2027/2809 ,  H01L2224/48175 ,  H01L2224/48195 ,  H01L2224/73265 ,  H01L2224/92247

Abstract: A power converter package includes a leadframe including first and second die pads, and supports connected to first leads, and second leads. A first semiconductor die including first bond pads is on the first die pad, and a second semiconductor die including second bond pads is on the second die pad. A transformer stack includes a top magnetic sheet and a bottom magnetic sheet on respective sides of a laminate substrate that includes a coil within, and coil contacts. A silicon block is attached to the bottom magnetic sheet and edges of the laminate substrate are attached to the supports. Bond wires are between the first bond pads and the second leads, the second bond pads and the second leads, and the first and second bond pads and the coil contacts. Mold encapsulates the respective semiconductor and the transformer stack. A bottom of the silicon block is exposed from the mold.

公开(公告)号：US12009280B2

公开(公告)日：2024-06-11

申请号：US17547698

申请日：2021-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rongwei Zhang ,  Woochan Kim ,  Patrick Francis Thompson

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/3677 ,  H01L21/4882 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/48138 ,  H01L2224/48158

Abstract: An integrated circuit (IC) package includes a molding having a first surface and a second surface, the first surface opposing the second surface. An interconnect is encased in the molding. The interconnect includes pads situated at a periphery of a side of the IC package. A portion of the pads are exposed at the first surface of the molding. A die pad is situated proximal to the second surface of the molding. The die pad has a first surface and a second surface, the first surface opposing the second surface, and the second surface is circumscribed by the second surface of the molding. A die is mounted on the first surface of the die pad. A heat spreader is mounted on the second surface of the molding and the second surface of the die pad. The heat spreader extends between edges of the second surface of the molding.

公开(公告)号：US20230207420A1

公开(公告)日：2023-06-29

申请号：US17563789

申请日：2021-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kwang-Soo Kim ,  Vivek Kishorechand Arora ,  Woochan Kim

IPC: H01L23/373 ,  H01L29/20 ,  H01L29/772

CPC classification number: H01L23/3738 ,  H01L23/3731 ,  H01L29/2003 ,  H01L29/772

Abstract: An electronic device for use in power related applications includes a multi-layered substrate comprised of a first metal layer, a second metal layer, and an intermediate layer disposed between the first metal layer, and the second metal layer. The first metal layer is partitioned into sections, where each of the sections has a first surface and electrical circuits patterned onto the first surface. A lead frame is attached to outer portions of the first metal layer and a die is attached to the first surface of each of the sections of the first metal layer.

公开(公告)号：US20220238424A1

公开(公告)日：2022-07-28

申请号：US17719246

申请日：2022-04-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anindya Poddar ,  Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16

Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.

公开(公告)号：US11183460B2

公开(公告)日：2021-11-23

申请号：US16132906

申请日：2018-09-17

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Mutsumi Masumoto ,  Kengo Aoya ,  Vivek Kishorechand Arora ,  Anindya Poddar

IPC: H01L23/538 ,  H01L23/373 ,  H01L21/56 ,  H01L23/498

Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.

公开(公告)号：US20210013138A1

公开(公告)日：2021-01-14

申请号：US16504816

申请日：2019-07-08

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Vivek Arora ,  Ken Pham

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/64 ,  H01L21/48 ,  H01L21/56

Abstract: A stacked die semiconductor package includes a leadframe including a die pad and lead terminals on at least two sides of the die pad, a top die having circuitry coupled to bond pads, and bottom die having a back side that is attached by die attach material to the die pad and a top side having at least one redistribution layer (RDL) over and coupled to a top metal level including connections to input/output (IO) nodes on the top metal level. The RDL provides a metal pattern including wirebond pads that match locations of the bond pads of the top die. The bond pads on the top die are flip-chip attached to the wirebond pads of the bottom die, and the bond wires are positioned between the wirebond pads and the lead terminals.

公开(公告)号：US20200381322A1

公开(公告)日：2020-12-03

申请号：US16996742

申请日：2020-08-18

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Vivek Aurora ,  Anindya Poddar

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/56

Abstract: In a described example a device includes: a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface; a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall; a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; and portions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer.

公开(公告)号：US10748827B2

公开(公告)日：2020-08-18

申请号：US16120922

申请日：2018-09-04

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Vivek Arora ,  Anindya Poddar

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/56

Abstract: In a described example a device includes: a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface; a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall; a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; and portions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer.

公开(公告)号：US20200161225A1

公开(公告)日：2020-05-21

申请号：US16751088

申请日：2020-01-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anindya Poddar ,  Thomas Dyer Bonifield ,  Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/532

Abstract: Described herein is a technology or a method for fabricating a flip-chip on lead (FOL) semiconductor package. A lead frame includes an edge on surface that has a geometric shape that provides a radial and uniform distribution of electric fields. By placing the formed geometric shape along an active die of a semiconductor chip, the electric fields that are present in between the lead frame and the semiconductor chip are uniformly concentrated.

公开(公告)号：US12136588B2

公开(公告)日：2024-11-05

申请号：US17379934

申请日：2021-07-19

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/482

Abstract: A semiconductor package includes a leadframe including leads and a die attach pad (DAP) inside the leads, and at least one semiconductor die having a top side including circuitry electrically connected to bond pads and a bottom side attached to a bottom side portion of the DAP. The package includes a mold compound and a heat slug having a top side and a bottom side positioned within a cavity defined by sidewalls of the mold compound. The heat slug has an area greater than an area of the DAP is attached by its bottom side with a thermally conductive adhesive material to a top side portion of the DAP. Bondwires are between the leads and the bond pads. Exposed from the mold compound is a bottom side surfaces of the leads and the top side of the heat slug.