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    Heterojunction semiconductor device having high blocking capability
    2.
    发明授权
    Heterojunction semiconductor device having high blocking capability 有权

    公开(公告)号：US11322606B2

    公开(公告)日：2022-05-03

    申请号：US16969437

    申请日：2019-10-21

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weifeng Sun ,  Siyang Liu ,  Sheng Li ,  Chi Zhang ,  Xinyi Tao ,  Ningbo Li ,  Longxing Shi

    IPC: H01L29/778

    Abstract: A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.

    Bi-directional adaptive clocking circuit supporting a wide frequency range
    3.
    发明授权
    Bi-directional adaptive clocking circuit supporting a wide frequency range 有权

    公开(公告)号：US11139805B1

    公开(公告)日：2021-10-05

    申请号：US16957724

    申请日：2019-07-09

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weiwei Shan ,  Jun Yang ,  Longxing Shi

    IPC: H03K5/14 ,  H03K5/131 ,  G04F10/00 ,  H03K5/00 ,  G06F1/08

    Abstract: A two-way adaptive clock circuit supporting a wide frequency range is composed of a phase clock generating module, a phase clock selecting module, an adaptive clock stretching or compressing amount regulating circuit module and a control module. The adaptive clock stretching or compressing amount regulating circuit module can monitor delay information of a critical path in a chip in real time and feed the information back into the control module. After receiving a clock stretching or compressing enable signal and a stretching or compressing scale signal, the control module selects a target phase clock from clocks generated by the phase clock generating module to rapidly regulate an adaptive clock in a current cycle. The present invention is applied to an adaptive voltage frequency regulating circuit based on on-line time sequence monitoring.

    PVTM-based wide voltage range clock stretching circuit
    4.
    发明授权
    PVTM-based wide voltage range clock stretching circuit 有权

    公开(公告)号：US10033362B1

    公开(公告)日：2018-07-24

    申请号：US15562893

    申请日：2017-02-24

    Applicant: Southeast University

    Inventor： Weiwei Shan ,  Liang Wan ,  Longxing Shi

    IPC: H03H11/26 ,  H03K5/133 ,  H03L7/18

    Abstract: A PVTM-based wide voltage range clock stretching circuit is disclosed. The circuit consists of a PVTM circuit module, a phase clock generation module, a clock synchronization selection module and a control module. The PVTM circuit module monitors in real time the delay information of an on-chip delay unit to monitor the operating environment of the circuit, and feeds the delay information back to the control module. Under the control of a clock stretching enable signal and a clock stretching extent signal, the control module selects a target phase clock from the clocks generated by the phase clock generation module in accordance with the feedback from the PVTM, enabling the stretching of system clock within a single cycle in different PVT conditions. Sophisticated gate devices are not required, and the cost of area and power consumption are kept to minimal.

    Process Corner Detection Circuit Based on Self-Timing Oscillation Ring
    6.
    发明申请
    Process Corner Detection Circuit Based on Self-Timing Oscillation Ring 审中-公开

    公开(公告)号：US20170219649A1

    公开(公告)日：2017-08-03

    申请号：US15321111

    申请日：2014-12-26

    Applicant: Southeast University

    Inventor： Weiwei Shan ,  Longxing Shi ,  Jun Yang

    IPC: G01R31/28 ,  H03K3/03

    Abstract: A process corner detection circuit based on a self-timing oscillation ring comprises a reset circuit (1), the self-timing oscillation ring (2), and a counting module (3). The self-timing oscillation ring (2) consists of m two-input Miller units and inverters, and a two-input AND gate, m being a positive integer greater than or equal to 3. The circuit can be used for detecting a process corner of a fabricated integrated circuit chip, and reflecting the process corner of the chip according to the number of oscillations of the self-timing oscillation ring (2). The number of oscillations of the self-timing oscillation ring (2) in different process corners is acquired by Hspice simulation before the chip tape-out, and the process corner of the chip after the chip tape-out can be determined according to the actually measured number of oscillations.

    High-current N-type silicon-on-insulator lateral insulated-gate bipolar transistor
    8.
    发明授权
    High-current N-type silicon-on-insulator lateral insulated-gate bipolar transistor 有权
    大电流N型绝缘体上半导体绝缘栅双极晶体管

    公开(公告)号：US09159818B2

    公开(公告)日：2015-10-13

    申请号：US14349632

    申请日：2012-10-24

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weifeng Sun ,  Siyang Liu ,  Jing Zhu ,  Qinsong Qian ,  Shen Xu ,  Shengli Lu ,  Longxing Shi

    IPC: H01L27/24 ,  H01L29/739 ,  H01L29/40 ,  H01L27/12 ,  H01L29/06 ,  H01L27/06

    CPC classification number: H01L29/7394 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/0638 ,  H01L29/404

    Abstract: A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor.

    Abstract translation: 一种高电流，N型绝缘体上的横向绝缘栅双极晶体管，包括：P型衬底，设置在P型衬底上的掩埋氧化物层，设置在P型衬底上的N型外延层 氧化物层和N型缓冲阱捕获区。 P型体区域和N型中央缓冲区捕获区域设置在N型外延层内部; P型漏极区域设置在缓冲陷阱区域中; N型源极区域和P型体接触区域设置在P型体区域中; N型基极区域和P型发射极区域设置在缓冲陷阱区域中; 栅极和场氧化物层设置在N型外延层上; 多晶硅栅极设置在栅极氧化物层上; 并且钝化层和金属层设置在对称晶体管的表面上。 改善P型发射极区域的输出和电流密度，而不增加晶体管的面积。

    ISOLATION STRUCTURE OF HIGH-VOLTAGE DRIVING CIRCUIT
    9.
    发明申请
    ISOLATION STRUCTURE OF HIGH-VOLTAGE DRIVING CIRCUIT 有权
    高压驱动电路隔离结构

    公开(公告)号：US20140203406A1

    公开(公告)日：2014-07-24

    申请号：US14240287

    申请日：2012-08-14

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Longxing Shi ,  Qinsong Qian ,  Weifeng Sun ,  Jing Zhu ,  Xianguo Huang ,  Shengli Lu

    IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/761

    CPC classification number: H01L29/0646 ,  H01L21/265 ,  H01L21/761 ,  H01L21/823481 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/7835

    Abstract: An isolation structure of a high-voltage driving circuit includes a P-type substrate and a P-type epitaxial layer; a high voltage area, a low voltage area and a high and low voltage junction terminal area are arranged on the P-type epitaxial layer; a first P-type junction isolation area is arranged between the high and low voltage junction terminal area and the low voltage area, and a high-voltage insulated gate field effect tube is arranged between the high voltage area and the low voltage area; two sides of the high-voltage insulated gate field effect tube and an isolation structure between the high-voltage insulated gate field effect tube and a high side area are formed as a second P-type junction isolation area.

    Abstract translation: 高电压驱动电路的隔离结构包括P型衬底和P型外延层; 在P型外延层上布置有高电压区域，低电压区域和高低压端子区域; 在高低压区和低电压区之间设置第一P型结隔离区，高电压区与低压区之间设置高压绝缘栅场效应管; 高压绝缘栅场效应管的两侧和高压绝缘栅场效应管与高边区之间的隔离结构形成为第二P型结隔离区。

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